arch/arm/mach-socfpga/misc_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <env.h>
   9 #include <errno.h>
  10 #include <fdtdec.h>
  11 #include <linux/libfdt.h>
  12 #include <altera.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <watchdog.h>
  16 #include <asm/arch/misc.h>
  17 #include <asm/arch/reset_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20 #include <asm/arch/system_manager.h>
  21 #include <asm/arch/nic301.h>
  22 #include <asm/arch/scu.h>
  23 #include <asm/pl310.h>
  24
  25 #include <dt-bindings/reset/altr,rst-mgr.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 static struct pl310_regs *const pl310 =
  30         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  31 static struct socfpga_system_manager *sysmgr_regs =
  32         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  33 static struct nic301_registers *nic301_regs =
  34         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  35 static struct scu_registers *scu_regs =
  36         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  37
  38 /*
  39  * FPGA programming support for SoC FPGA Cyclone V
  40  */
  41 static Altera_desc altera_fpga[] = {
  42         {
  43                 /* Family */
  44                 Altera_SoCFPGA,
  45                 /* Interface type */
  46                 fast_passive_parallel,
  47                 /* No limitation as additional data will be ignored */
  48                 -1,
  49                 /* No device function table */
  50                 NULL,
  51                 /* Base interface address specified in driver */
  52                 NULL,
  53                 /* No cookie implementation */
  54                 0
  55         },
  56 };
  57
  58 static const struct {
  59         const u16       pn;
  60         const char      *name;
  61         const char      *var;
  62 } socfpga_fpga_model[] = {
  63         /* Cyclone V E */
  64         { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
  65         { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
  66         { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
  67         { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
  68         { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
  69         /* Cyclone V GX/GT */
  70         { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
  71         { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
  72         { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
  73         { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
  74         { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
  75         /* Cyclone V SE/SX/ST */
  76         { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
  77         { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
  78         { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
  79         { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
  80         /* Arria V */
  81         { 0x2d03, "Arria V, D5", "av_d5" },
  82 };
  83
  84 static int socfpga_fpga_id(const bool print_id)
  85 {
  86         const u32 altera_mi = 0x6e;
  87         const u32 id = scan_mgr_get_fpga_id();
  88
  89         const u32 lsb = id & 0x00000001;
  90         const u32 mi = (id >> 1) & 0x000007ff;
  91         const u32 pn = (id >> 12) & 0x0000ffff;
  92         const u32 version = (id >> 28) & 0x0000000f;
  93         int i;
  94
  95         if ((mi != altera_mi) || (lsb != 1)) {
  96                 printf("FPGA:  Not Altera chip ID\n");
  97                 return -EINVAL;
  98         }
  99
 100         for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
 101                 if (pn == socfpga_fpga_model[i].pn)
 102                         break;
 103
 104         if (i == ARRAY_SIZE(socfpga_fpga_model)) {
 105                 printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
 106                 return -EINVAL;
 107         }
 108
 109         if (print_id)
 110                 printf("FPGA:  Altera %s, version 0x%01x\n",
 111                        socfpga_fpga_model[i].name, version);
 112         return i;
 113 }
 114
 115 /*
 116  * Print CPU information
 117  */
 118 #if defined(CONFIG_DISPLAY_CPUINFO)
 119 int print_cpuinfo(void)
 120 {
 121         const u32 bsel =
 122                 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
 123
 124         puts("CPU:   Altera SoCFPGA Platform\n");
 125         socfpga_fpga_id(1);
 126
 127         printf("BOOT:  %s\n", bsel_str[bsel].name);
 128         return 0;
 129 }
 130 #endif
 131
 132 #ifdef CONFIG_ARCH_MISC_INIT
 133 int arch_misc_init(void)
 134 {
 135         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 136         const int fpga_id = socfpga_fpga_id(0);
 137         env_set("bootmode", bsel_str[bsel].mode);
 138         if (fpga_id >= 0)
 139                 env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
 140         return 0;
 141 }
 142 #endif
 143
 144 /*
 145  * Convert all NIC-301 AMBA slaves from secure to non-secure
 146  */
 147 static void socfpga_nic301_slave_ns(void)
 148 {
 149         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 150         writel(0x1, &nic301_regs->hps2fpgaregs);
 151         writel(0x1, &nic301_regs->acp);
 152         writel(0x1, &nic301_regs->rom);
 153         writel(0x1, &nic301_regs->ocram);
 154         writel(0x1, &nic301_regs->sdrdata);
 155 }
 156
 157 void socfpga_sdram_remap_zero(void)
 158 {
 159         u32 remap;
 160
 161         socfpga_nic301_slave_ns();
 162
 163         /*
 164          * Private components security:
 165          * U-Boot : configure private timer, global timer and cpu component
 166          * access as non secure for kernel stage (as required by Linux)
 167          */
 168         setbits_le32(&scu_regs->sacr, 0xfff);
 169
 170         /* Configure the L2 controller to make SDRAM start at 0 */
 171         remap = 0x1; /* remap.mpuzero */
 172         /* Keep fpga bridge enabled when running from FPGA onchip RAM */
 173         if (socfpga_is_booting_from_fpga())
 174                 remap |= 0x8; /* remap.hps2fpga */
 175         writel(remap, &nic301_regs->remap);
 176
 177         writel(0x1, &pl310->pl310_addr_filter_start);
 178 }
 179
 180 static u32 iswgrp_handoff[8];
 181
 182 int arch_early_init_r(void)
 183 {
 184         int i;
 185
 186         /*
 187          * Write magic value into magic register to unlock support for
 188          * issuing warm reset. The ancient kernel code expects this
 189          * value to be written into the register by the bootloader, so
 190          * to support that old code, we write it here instead of in the
 191          * reset_cpu() function just before resetting the CPU.
 192          */
 193         writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
 194
 195         for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
 196                 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
 197
 198         socfpga_bridges_reset(1);
 199
 200         socfpga_sdram_remap_zero();
 201
 202         /* Add device descriptor to FPGA device table */
 203         socfpga_fpga_add(&altera_fpga[0]);
 204
 205         return 0;
 206 }
 207
 208 #ifndef CONFIG_SPL_BUILD
 209 static struct socfpga_reset_manager *reset_manager_base =
 210         (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
 211 static struct socfpga_sdr_ctrl *sdr_ctrl =
 212         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 213
 214 void do_bridge_reset(int enable, unsigned int mask)
 215 {
 216         int i;
 217
 218         if (enable) {
 219                 socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
 220                                                  !(mask & BIT(1)),
 221                                                  !(mask & BIT(2)));
 222                 for (i = 0; i < 2; i++) {       /* Reload SW setting cache */
 223                         iswgrp_handoff[i] =
 224                                 readl(&sysmgr_regs->iswgrp_handoff[i]);
 225                 }
 226
 227                 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
 228                 writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
 229                 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
 230                 writel(iswgrp_handoff[1], &nic301_regs->remap);
 231         } else {
 232                 writel(0, &sysmgr_regs->fpgaintfgrp_module);
 233                 writel(0, &sdr_ctrl->fpgaport_rst);
 234                 writel(0, &reset_manager_base->brg_mod_reset);
 235                 writel(1, &nic301_regs->remap);
 236         }
 237 }
 238 #endif