arch/arm/mach-socfpga/misc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <linux/libfdt.h>
  11 #include <altera.h>
  12 #include <miiphy.h>
  13 #include <netdev.h>
  14 #include <watchdog.h>
  15 #include <asm/arch/misc.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <asm/arch/scan_manager.h>
  18 #include <asm/arch/system_manager.h>
  19 #include <asm/arch/nic301.h>
  20 #include <asm/arch/scu.h>
  21 #include <asm/pl310.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #ifdef CONFIG_SYS_L2_PL310
  26 static const struct pl310_regs *const pl310 =
  27         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  28 #endif
  29
  30 struct bsel bsel_str[] = {
  31         { "rsvd", "Reserved", },
  32         { "fpga", "FPGA (HPS2FPGA Bridge)", },
  33         { "nand", "NAND Flash (1.8V)", },
  34         { "nand", "NAND Flash (3.0V)", },
  35         { "sd", "SD/MMC External Transceiver (1.8V)", },
  36         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  37         { "qspi", "QSPI Flash (1.8V)", },
  38         { "qspi", "QSPI Flash (3.0V)", },
  39 };
  40
  41 int dram_init(void)
  42 {
  43         if (fdtdec_setup_mem_size_base() != 0)
  44                 return -EINVAL;
  45
  46         return 0;
  47 }
  48
  49 void enable_caches(void)
  50 {
  51 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  52         icache_enable();
  53 #endif
  54 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  55         dcache_enable();
  56 #endif
  57 }
  58
  59 #ifdef CONFIG_SYS_L2_PL310
  60 void v7_outer_cache_enable(void)
  61 {
  62         struct udevice *dev;
  63
  64         if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  65                 pr_err("cache controller driver NOT found!\n");
  66 }
  67
  68 void v7_outer_cache_disable(void)
  69 {
  70         /* Disable the L2 cache */
  71         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  72 }
  73
  74 void socfpga_pl310_clear(void)
  75 {
  76         u32 mask = 0xff, ena = 0;
  77
  78         icache_enable();
  79
  80         /* Disable the L2 cache */
  81         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  82
  83         writel(0x0, &pl310->pl310_tag_latency_ctrl);
  84         writel(0x10, &pl310->pl310_data_latency_ctrl);
  85
  86         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  87         setbits_le32(&pl310->pl310_aux_ctrl,
  88                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  89                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  90                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  91
  92         /* Enable the L2 cache */
  93         ena = readl(&pl310->pl310_ctrl);
  94         ena |= L2X0_CTRL_EN;
  95
  96         /*
  97          * Invalidate the PL310 L2 cache. Keep the invalidation code
  98          * entirely in L1 I-cache to avoid any bus traffic through
  99          * the L2.
 100          */
 101         asm volatile(
 102                 ".align 5                       \n"
 103                 "       b       3f              \n"
 104                 "1:     str     %1,     [%4]    \n"
 105                 "       dsb                     \n"
 106                 "       isb                     \n"
 107                 "       str     %0,     [%2]    \n"
 108                 "       dsb                     \n"
 109                 "       isb                     \n"
 110                 "2:     ldr     %0,     [%2]    \n"
 111                 "       cmp     %0,     #0      \n"
 112                 "       bne     2b              \n"
 113                 "       str     %0,     [%3]    \n"
 114                 "       dsb                     \n"
 115                 "       isb                     \n"
 116                 "       b       4f              \n"
 117                 "3:     b       1b              \n"
 118                 "4:     nop                     \n"
 119         : "+r"(mask), "+r"(ena)
 120         : "r"(&pl310->pl310_inv_way),
 121           "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
 122         : "memory", "cc");
 123
 124         /* Disable the L2 cache */
 125         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 126 }
 127 #endif
 128
 129 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 130 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 131 int overwrite_console(void)
 132 {
 133         return 0;
 134 }
 135 #endif
 136
 137 #ifdef CONFIG_FPGA
 138 /* add device descriptor to FPGA device table */
 139 void socfpga_fpga_add(void *fpga_desc)
 140 {
 141         fpga_init();
 142         fpga_add(fpga_altera, fpga_desc);
 143 }
 144 #endif
 145
 146 int arch_cpu_init(void)
 147 {
 148 #ifdef CONFIG_HW_WATCHDOG
 149         /*
 150          * In case the watchdog is enabled, make sure to (re-)configure it
 151          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 152          * timeout value is still active which might too short for Linux
 153          * booting.
 154          */
 155         hw_watchdog_init();
 156 #else
 157         /*
 158          * If the HW watchdog is NOT enabled, make sure it is not running,
 159          * for example because it was enabled in the preloader. This might
 160          * trigger a watchdog-triggered reboot of Linux kernel later.
 161          * Toggle watchdog reset, so watchdog in not running state.
 162          */
 163         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 164         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 165 #endif
 166
 167         return 0;
 168 }
 169
 170 #ifndef CONFIG_SPL_BUILD
 171 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 172 {
 173         unsigned int mask = ~0;
 174
 175         if (argc < 2 || argc > 3)
 176                 return CMD_RET_USAGE;
 177
 178         argv++;
 179
 180         if (argc == 3)
 181                 mask = simple_strtoul(argv[1], NULL, 16);
 182
 183         switch (*argv[0]) {
 184         case 'e':       /* Enable */
 185                 do_bridge_reset(1, mask);
 186                 break;
 187         case 'd':       /* Disable */
 188                 do_bridge_reset(0, mask);
 189                 break;
 190         default:
 191                 return CMD_RET_USAGE;
 192         }
 193
 194         return 0;
 195 }
 196
 197 U_BOOT_CMD(bridge, 3, 1, do_bridge,
 198            "SoCFPGA HPS FPGA bridge control",
 199            "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 200            "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 201            ""
 202 );
 203
 204 #endif