arch/arm/mach-socfpga/misc.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <errno.h>
  10 #include <fdtdec.h>
  11 #include <libfdt.h>
  12 #include <altera.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <watchdog.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <asm/arch/scan_manager.h>
  18 #include <asm/arch/system_manager.h>
  19 #include <asm/arch/dwmmc.h>
  20 #include <asm/arch/nic301.h>
  21 #include <asm/arch/scu.h>
  22 #include <asm/pl310.h>
  23
  24 #include <dt-bindings/reset/altr,rst-mgr.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static struct pl310_regs *const pl310 =
  29         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  30 static struct socfpga_system_manager *sysmgr_regs =
  31         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  32 static struct socfpga_reset_manager *reset_manager_base =
  33         (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
  34 static struct nic301_registers *nic301_regs =
  35         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  36 static struct scu_registers *scu_regs =
  37         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  38
  39 int dram_init(void)
  40 {
  41         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  42         return 0;
  43 }
  44
  45 void enable_caches(void)
  46 {
  47 #ifndef CONFIG_SYS_ICACHE_OFF
  48         icache_enable();
  49 #endif
  50 #ifndef CONFIG_SYS_DCACHE_OFF
  51         dcache_enable();
  52 #endif
  53 }
  54
  55 void v7_outer_cache_enable(void)
  56 {
  57         /* Disable the L2 cache */
  58         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  59
  60         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  61         setbits_le32(&pl310->pl310_aux_ctrl,
  62                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  63                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  64                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  65
  66         /* Enable the L2 cache */
  67         setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  68 }
  69
  70 void v7_outer_cache_disable(void)
  71 {
  72         /* Disable the L2 cache */
  73         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  74 }
  75
  76 /*
  77  * DesignWare Ethernet initialization
  78  */
  79 #ifdef CONFIG_ETH_DESIGNWARE
  80 static void dwmac_deassert_reset(const unsigned int of_reset_id)
  81 {
  82         u32 physhift, reset;
  83
  84         if (of_reset_id == EMAC0_RESET) {
  85                 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  86                 reset = SOCFPGA_RESET(EMAC0);
  87         } else if (of_reset_id == EMAC1_RESET) {
  88                 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  89                 reset = SOCFPGA_RESET(EMAC1);
  90         } else {
  91                 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
  92                 return;
  93         }
  94
  95         /* Clearing emac0 PHY interface select to 0 */
  96         clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
  97                      SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
  98
  99         /* configure to PHY interface select choosed */
 100         setbits_le32(&sysmgr_regs->emacgrp_ctrl,
 101                      SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
 102
 103         /* Release the EMAC controller from reset */
 104         socfpga_per_reset(reset, 0);
 105 }
 106
 107 int cpu_eth_init(bd_t *bis)
 108 {
 109         const void *fdt = gd->fdt_blob;
 110         struct fdtdec_phandle_args args;
 111         int nodes[2];   /* Max. two GMACs */
 112         int ret, count;
 113         int i, node;
 114
 115         /* Put both GMACs into RESET state. */
 116         socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
 117         socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
 118
 119         count = fdtdec_find_aliases_for_id(fdt, "ethernet",
 120                                            COMPAT_ALTERA_SOCFPGA_DWMAC,
 121                                            nodes, ARRAY_SIZE(nodes));
 122         for (i = 0; i < count; i++) {
 123                 node = nodes[i];
 124                 if (node <= 0)
 125                         continue;
 126
 127                 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
 128                                                      "#reset-cells", 1, 0,
 129                                                      &args);
 130                 if (ret || (args.args_count != 1)) {
 131                         debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
 132                         continue;
 133                 }
 134
 135                 dwmac_deassert_reset(args.args[0]);
 136         }
 137
 138         return 0;
 139 }
 140 #endif
 141
 142 struct {
 143         const char      *mode;
 144         const char      *name;
 145 } bsel_str[] = {
 146         { "rsvd", "Reserved", },
 147         { "fpga", "FPGA (HPS2FPGA Bridge)", },
 148         { "nand", "NAND Flash (1.8V)", },
 149         { "nand", "NAND Flash (3.0V)", },
 150         { "sd", "SD/MMC External Transceiver (1.8V)", },
 151         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
 152         { "qspi", "QSPI Flash (1.8V)", },
 153         { "qspi", "QSPI Flash (3.0V)", },
 154 };
 155
 156 static const struct {
 157         const u16       pn;
 158         const char      *name;
 159         const char      *var;
 160 } const socfpga_fpga_model[] = {
 161         /* Cyclone V E */
 162         { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
 163         { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
 164         { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
 165         { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
 166         { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
 167         /* Cyclone V GX/GT */
 168         { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
 169         { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
 170         { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
 171         { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
 172         { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
 173         /* Cyclone V SE/SX/ST */
 174         { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
 175         { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
 176         { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
 177         { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
 178         /* Arria V */
 179         { 0x2d03, "Arria V, D5", "av_d5" },
 180 };
 181
 182 static int socfpga_fpga_id(const bool print_id)
 183 {
 184         const u32 altera_mi = 0x6e;
 185         const u32 id = scan_mgr_get_fpga_id();
 186
 187         const u32 lsb = id & 0x00000001;
 188         const u32 mi = (id >> 1) & 0x000007ff;
 189         const u32 pn = (id >> 12) & 0x0000ffff;
 190         const u32 version = (id >> 28) & 0x0000000f;
 191         int i;
 192
 193         if ((mi != altera_mi) || (lsb != 1)) {
 194                 printf("FPGA:  Not Altera chip ID\n");
 195                 return -EINVAL;
 196         }
 197
 198         for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
 199                 if (pn == socfpga_fpga_model[i].pn)
 200                         break;
 201
 202         if (i == ARRAY_SIZE(socfpga_fpga_model)) {
 203                 printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
 204                 return -EINVAL;
 205         }
 206
 207         if (print_id)
 208                 printf("FPGA:  Altera %s, version 0x%01x\n",
 209                        socfpga_fpga_model[i].name, version);
 210         return i;
 211 }
 212
 213 /*
 214  * Print CPU information
 215  */
 216 #if defined(CONFIG_DISPLAY_CPUINFO)
 217 int print_cpuinfo(void)
 218 {
 219         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 220         puts("CPU:   Altera SoCFPGA Platform\n");
 221         socfpga_fpga_id(1);
 222         printf("BOOT:  %s\n", bsel_str[bsel].name);
 223         return 0;
 224 }
 225 #endif
 226
 227 #ifdef CONFIG_ARCH_MISC_INIT
 228 int arch_misc_init(void)
 229 {
 230         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 231         const int fpga_id = socfpga_fpga_id(0);
 232         setenv("bootmode", bsel_str[bsel].mode);
 233         if (fpga_id >= 0)
 234                 setenv("fpgatype", socfpga_fpga_model[fpga_id].var);
 235         return 0;
 236 }
 237 #endif
 238
 239 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 240 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 241 int overwrite_console(void)
 242 {
 243         return 0;
 244 }
 245 #endif
 246
 247 #ifdef CONFIG_FPGA
 248 /*
 249  * FPGA programming support for SoC FPGA Cyclone V
 250  */
 251 static Altera_desc altera_fpga[] = {
 252         {
 253                 /* Family */
 254                 Altera_SoCFPGA,
 255                 /* Interface type */
 256                 fast_passive_parallel,
 257                 /* No limitation as additional data will be ignored */
 258                 -1,
 259                 /* No device function table */
 260                 NULL,
 261                 /* Base interface address specified in driver */
 262                 NULL,
 263                 /* No cookie implementation */
 264                 0
 265         },
 266 };
 267
 268 /* add device descriptor to FPGA device table */
 269 static void socfpga_fpga_add(void)
 270 {
 271         int i;
 272         fpga_init();
 273         for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
 274                 fpga_add(fpga_altera, &altera_fpga[i]);
 275 }
 276 #else
 277 static inline void socfpga_fpga_add(void) {}
 278 #endif
 279
 280 int arch_cpu_init(void)
 281 {
 282 #ifdef CONFIG_HW_WATCHDOG
 283         /*
 284          * In case the watchdog is enabled, make sure to (re-)configure it
 285          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 286          * timeout value is still active which might too short for Linux
 287          * booting.
 288          */
 289         hw_watchdog_init();
 290 #else
 291         /*
 292          * If the HW watchdog is NOT enabled, make sure it is not running,
 293          * for example because it was enabled in the preloader. This might
 294          * trigger a watchdog-triggered reboot of Linux kernel later.
 295          * Toggle watchdog reset, so watchdog in not running state.
 296          */
 297         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 298         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 299 #endif
 300
 301         return 0;
 302 }
 303
 304 /*
 305  * Convert all NIC-301 AMBA slaves from secure to non-secure
 306  */
 307 static void socfpga_nic301_slave_ns(void)
 308 {
 309         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 310         writel(0x1, &nic301_regs->hps2fpgaregs);
 311         writel(0x1, &nic301_regs->acp);
 312         writel(0x1, &nic301_regs->rom);
 313         writel(0x1, &nic301_regs->ocram);
 314         writel(0x1, &nic301_regs->sdrdata);
 315 }
 316
 317 static uint32_t iswgrp_handoff[8];
 318
 319 int arch_early_init_r(void)
 320 {
 321         int i;
 322
 323         /*
 324          * Write magic value into magic register to unlock support for
 325          * issuing warm reset. The ancient kernel code expects this
 326          * value to be written into the register by the bootloader, so
 327          * to support that old code, we write it here instead of in the
 328          * reset_cpu() function just before reseting the CPU.
 329          */
 330         writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
 331
 332         for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
 333                 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
 334
 335         socfpga_bridges_reset(1);
 336         socfpga_nic301_slave_ns();
 337
 338         /*
 339          * Private components security:
 340          * U-Boot : configure private timer, global timer and cpu component
 341          * access as non secure for kernel stage (as required by Linux)
 342          */
 343         setbits_le32(&scu_regs->sacr, 0xfff);
 344
 345         /* Configure the L2 controller to make SDRAM start at 0 */
 346 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 347         writel(0x2, &nic301_regs->remap);
 348 #else
 349         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 350         writel(0x1, &pl310->pl310_addr_filter_start);
 351 #endif
 352
 353         /* Add device descriptor to FPGA device table */
 354         socfpga_fpga_add();
 355
 356 #ifdef CONFIG_DESIGNWARE_SPI
 357         /* Get Designware SPI controller out of reset */
 358         socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
 359         socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
 360 #endif
 361
 362 #ifdef CONFIG_NAND_DENALI
 363         socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
 364 #endif
 365
 366         return 0;
 367 }
 368
 369 static void socfpga_sdram_apply_static_cfg(void)
 370 {
 371         const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
 372         const uint32_t applymask = 0x8;
 373         uint32_t val = readl(staticcfg) | applymask;
 374
 375         /*
 376          * SDRAM staticcfg register specific:
 377          * When applying the register setting, the CPU must not access
 378          * SDRAM. Luckily for us, we can abuse i-cache here to help us
 379          * circumvent the SDRAM access issue. The idea is to make sure
 380          * that the code is in one full i-cache line by branching past
 381          * it and back. Once it is in the i-cache, we execute the core
 382          * of the code and apply the register settings.
 383          *
 384          * The code below uses 7 instructions, while the Cortex-A9 has
 385          * 32-byte cachelines, thus the limit is 8 instructions total.
 386          */
 387         asm volatile(
 388                 ".align 5                       \n"
 389                 "       b       2f              \n"
 390                 "1:     str     %0,     [%1]    \n"
 391                 "       dsb                     \n"
 392                 "       isb                     \n"
 393                 "       b       3f              \n"
 394                 "2:     b       1b              \n"
 395                 "3:     nop                     \n"
 396         : : "r"(val), "r"(staticcfg) : "memory", "cc");
 397 }
 398
 399 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 400 {
 401         if (argc != 2)
 402                 return CMD_RET_USAGE;
 403
 404         argv++;
 405
 406         switch (*argv[0]) {
 407         case 'e':       /* Enable */
 408                 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
 409                 socfpga_sdram_apply_static_cfg();
 410                 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
 411                 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
 412                 writel(iswgrp_handoff[1], &nic301_regs->remap);
 413                 break;
 414         case 'd':       /* Disable */
 415                 writel(0, &sysmgr_regs->fpgaintfgrp_module);
 416                 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
 417                 socfpga_sdram_apply_static_cfg();
 418                 writel(0, &reset_manager_base->brg_mod_reset);
 419                 writel(1, &nic301_regs->remap);
 420                 break;
 421         default:
 422                 return CMD_RET_USAGE;
 423         }
 424
 425         return 0;
 426 }
 427
 428 U_BOOT_CMD(
 429         bridge, 2, 1, do_bridge,
 430         "SoCFPGA HPS FPGA bridge control",
 431         "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 432         "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 433         ""
 434 );