1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
11 #include <asm/arch/mailbox_s10.h>
12 #include <asm/arch/system_manager.h>
13 #include <asm/secure.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define MBOX_READL(reg) \
18 readl(SOCFPGA_MAILBOX_ADDRESS + (reg))
20 #define MBOX_WRITEL(data, reg) \
21 writel(data, SOCFPGA_MAILBOX_ADDRESS + (reg))
23 #define MBOX_READ_RESP_BUF(rout) \
24 MBOX_READL(MBOX_RESP_BUF + ((rout) * sizeof(u32)))
26 #define MBOX_WRITE_CMD_BUF(data, cin) \
27 MBOX_WRITEL(data, MBOX_CMD_BUF + ((cin) * sizeof(u32)))
29 static __always_inline int mbox_polling_resp(u32 rout)
35 rin = MBOX_READL(MBOX_RIN);
45 /* Check for available slot and write to circular buffer.
46 * It also update command valid offset (cin) register.
48 static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
55 cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE;
56 cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE;
58 /* if command buffer is full or not enough free space
59 * to fit the data. Note, len is in u32 unit.
61 if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
62 ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
63 MBOX_CMD_BUFFER_SIZE) < (len + 1))
66 /* write header to circular buffer */
67 MBOX_WRITE_CMD_BUF(header, cin++);
68 /* wrapping around when it reach the buffer size */
69 cin %= MBOX_CMD_BUFFER_SIZE;
72 for (i = 0; i < len; i++) {
73 MBOX_WRITE_CMD_BUF(arg[i], cin++);
74 /* wrapping around when it reach the buffer size */
75 cin %= MBOX_CMD_BUFFER_SIZE;
78 /* write command valid offset */
79 MBOX_WRITEL(cin, MBOX_CIN);
84 /* Check the command and fill it into circular buffer */
85 static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
86 u8 is_indirect, u32 len,
92 /* Total length is command + argument length */
93 if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
96 if (cmd > MBOX_MAX_CMD_INDEX)
99 header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
100 (is_indirect) ? 1 : 0, cmd);
102 ret = mbox_fill_cmd_circular_buff(header, len, arg);
107 /* Send command only without waiting for responses from SDM */
108 static __always_inline int mbox_send_cmd_only_common(u8 id, u32 cmd,
109 u8 is_indirect, u32 len,
112 int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
114 MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
119 /* Return number of responses received in buffer */
120 static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
126 /* clear doorbell from SDM if it was SET */
127 if (MBOX_READL(MBOX_DOORBELL_FROM_SDM) & 1)
128 MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
130 /* read current response offset */
131 rout = MBOX_READL(MBOX_ROUT);
132 /* read response valid offset */
133 rin = MBOX_READL(MBOX_RIN);
135 while (rin != rout && (resp_len < resp_buf_max_len)) {
136 /* Response received */
138 resp_buf[resp_len++] = MBOX_READ_RESP_BUF(rout);
141 /* wrapping around when it reach the buffer size */
142 rout %= MBOX_RESP_BUFFER_SIZE;
143 /* update next ROUT */
144 MBOX_WRITEL(rout, MBOX_ROUT);
150 /* Support one command and up to 31 words argument length only */
151 static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect,
152 u32 len, u32 *arg, u8 urgent,
165 /* Read status because it is toggled */
166 status = MBOX_READL(MBOX_STATUS) & MBOX_STATUS_UA_MSK;
167 /* Write urgent command to urgent register */
168 MBOX_WRITEL(cmd, MBOX_URG);
170 ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
176 MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
181 /* Wait for doorbell from SDM */
182 while (!MBOX_READL(MBOX_DOORBELL_FROM_SDM) && ret--)
187 /* clear interrupt */
188 MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
191 u32 new_status = MBOX_READL(MBOX_STATUS);
193 /* Urgent ACK is toggled */
194 if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
200 /* read current response offset */
201 rout = MBOX_READL(MBOX_ROUT);
203 /* read response valid offset */
204 rin = MBOX_READL(MBOX_RIN);
207 /* Response received */
208 resp = MBOX_READ_RESP_BUF(rout);
210 /* wrapping around when it reach the buffer size */
211 rout %= MBOX_RESP_BUFFER_SIZE;
212 /* update next ROUT */
213 MBOX_WRITEL(rout, MBOX_ROUT);
215 /* check client ID and ID */
216 if ((MBOX_RESP_CLIENT_GET(resp) ==
217 MBOX_CLIENT_ID_UBOOT) &&
218 (MBOX_RESP_ID_GET(resp) == id)) {
219 ret = MBOX_RESP_ERR_GET(resp);
224 buf_len = *resp_buf_len;
230 resp_len = MBOX_RESP_LEN_GET(resp);
232 ret = mbox_polling_resp(rout);
235 /* we need to process response buffer
236 * even caller doesn't need it
238 resp = MBOX_READ_RESP_BUF(rout);
241 rout %= MBOX_RESP_BUFFER_SIZE;
242 MBOX_WRITEL(rout, MBOX_ROUT);
244 /* copy response to buffer */
245 resp_buf[*resp_buf_len] = resp;
262 /* enable mailbox interrupts */
263 MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
265 /* Ensure urgent request is cleared */
266 MBOX_WRITEL(0, MBOX_URG);
268 /* Ensure the Doorbell Interrupt is cleared */
269 MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
271 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
276 /* Renable mailbox interrupts after MBOX_RESTART */
277 MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
282 #ifdef CONFIG_CADENCE_QSPI
283 int mbox_qspi_close(void)
285 return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
286 0, NULL, 0, 0, NULL);
289 int mbox_qspi_open(void)
295 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
296 0, NULL, 0, 0, NULL);
298 /* retry again by closing and reopen the QSPI again */
299 ret = mbox_qspi_close();
303 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
304 MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
309 /* HPS will directly control the QSPI controller, no longer mailbox */
311 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
312 0, NULL, 0, (u32 *)&resp_buf_len,
317 /* We are getting QSPI ref clock and set into sysmgr boot register */
318 printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
320 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
329 #endif /* CONFIG_CADENCE_QSPI */
331 int mbox_reset_cold(void)
335 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
336 0, NULL, 0, 0, NULL);
338 /* mailbox sent failure, wait for watchdog to kick in */
344 /* Accepted commands: CONFIG_STATUS or RECONFIG_STATUS */
345 static __always_inline int mbox_get_fpga_config_status_common(u32 cmd)
347 u32 reconfig_status_resp_len;
348 u32 reconfig_status_resp[RECONFIG_STATUS_RESPONSE_LEN];
351 reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
352 ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd,
353 MBOX_CMD_DIRECT, 0, NULL, 0,
354 &reconfig_status_resp_len,
355 reconfig_status_resp);
360 /* Check for any error */
361 ret = reconfig_status_resp[RECONFIG_STATUS_STATE];
362 if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
365 /* Make sure nStatus is not 0 */
366 ret = reconfig_status_resp[RECONFIG_STATUS_PIN_STATUS];
367 if (!(ret & RCF_PIN_STATUS_NSTATUS))
368 return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
370 ret = reconfig_status_resp[RECONFIG_STATUS_SOFTFUNC_STATUS];
371 if (ret & RCF_SOFTFUNC_STATUS_SEU_ERROR)
372 return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
374 if ((ret & RCF_SOFTFUNC_STATUS_CONF_DONE) &&
375 (ret & RCF_SOFTFUNC_STATUS_INIT_DONE) &&
376 !reconfig_status_resp[RECONFIG_STATUS_STATE])
377 return 0; /* configuration success */
379 return MBOX_CFGSTAT_STATE_CONFIG;
382 int mbox_get_fpga_config_status(u32 cmd)
384 return mbox_get_fpga_config_status_common(cmd);
387 int __secure mbox_get_fpga_config_status_psci(u32 cmd)
389 return mbox_get_fpga_config_status_common(cmd);
392 int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
393 u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
395 return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
396 resp_buf_len, resp_buf);
399 int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
400 u32 *arg, u8 urgent, u32 *resp_buf_len,
403 return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
404 resp_buf_len, resp_buf);
407 int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
409 return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
412 int __secure mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
415 return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
418 int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
420 return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
423 int __secure mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len)
425 return __mbox_rcv_resp(resp_buf, resp_buf_max_len);