1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
7 #ifndef _CLOCK_MANAGER_S10_
8 #define _CLOCK_MANAGER_S10_
10 /* Clock speed accessors */
11 unsigned long cm_get_mpu_clk_hz(void);
12 unsigned long cm_get_sdram_clk_hz(void);
13 unsigned int cm_get_l4_sp_clk_hz(void);
14 unsigned int cm_get_mmc_controller_clk_hz(void);
15 unsigned int cm_get_qspi_controller_clk_hz(void);
16 unsigned int cm_get_spi_controller_clk_hz(void);
17 const unsigned int cm_get_osc_clk_hz(void);
18 const unsigned int cm_get_f2s_per_ref_clk_hz(void);
19 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
20 const unsigned int cm_get_intosc_clk_hz(void);
21 const unsigned int cm_get_fpga_clk_hz(void);
23 #define CLKMGR_EOSC1_HZ 25000000
24 #define CLKMGR_INTOSC_HZ 460000000
25 #define CLKMGR_FPGA_CLK_HZ 50000000
27 /* Clock configuration accessors */
28 const struct cm_config * const cm_get_default_config(void);
34 u32 main_pll_cntr2clk;
35 u32 main_pll_cntr3clk;
36 u32 main_pll_cntr4clk;
37 u32 main_pll_cntr5clk;
38 u32 main_pll_cntr6clk;
39 u32 main_pll_cntr7clk;
40 u32 main_pll_cntr8clk;
41 u32 main_pll_cntr9clk;
49 /* peripheral group */
70 void cm_basic_init(const struct cm_config * const cfg);
72 struct socfpga_clock_manager_main_pll {
97 u32 _pad_0x90_0xA0[5];
100 struct socfpga_clock_manager_per_pll {
124 u32 _pad_0x100_0x124[10];
127 struct socfpga_clock_manager {
137 u32 _pad_0x24_0x2c[3];
138 struct socfpga_clock_manager_main_pll main_pll;
139 struct socfpga_clock_manager_per_pll per_pll;
142 #define CLKMGR_CTRL_SAFEMODE BIT(0)
143 #define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
144 #define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f
146 #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
147 #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
148 #define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
149 #define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
150 #define CLKMGR_STAT_BUSY BIT(0)
151 #define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
152 #define CLKMGR_STAT_PERPLL_LOCKED BIT(9)
154 #define CLKMGR_PLLGLOB_PD_MASK 0x00000001
155 #define CLKMGR_PLLGLOB_RST_MASK 0x00000002
156 #define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3
157 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
158 #define CLKMGR_VCO_PSRC_EOSC1 0
159 #define CLKMGR_VCO_PSRC_INTOSC 1
160 #define CLKMGR_VCO_PSRC_F2S 2
161 #define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f
162 #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
164 #define CLKMGR_CLKSRC_MASK 0x7
165 #define CLKMGR_CLKSRC_OFFSET 16
166 #define CLKMGR_CLKSRC_MAIN 0
167 #define CLKMGR_CLKSRC_PER 1
168 #define CLKMGR_CLKSRC_OSC1 2
169 #define CLKMGR_CLKSRC_INTOSC 3
170 #define CLKMGR_CLKSRC_FPGA 4
171 #define CLKMGR_CLKCNT_MSK 0x7ff
173 #define CLKMGR_FDBCK_MDIV_MASK 0xff
174 #define CLKMGR_FDBCK_MDIV_OFFSET 24
176 #define CLKMGR_PLLC0_DIV_MASK 0xff
177 #define CLKMGR_PLLC1_DIV_MASK 0xff
178 #define CLKMGR_PLLC0_EN_OFFSET 27
179 #define CLKMGR_PLLC1_EN_OFFSET 24
181 #define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
182 #define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
183 #define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
184 #define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
185 #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
186 #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
188 #define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3
189 #define CLKMGR_NOCDIV_DIV1 0
190 #define CLKMGR_NOCDIV_DIV2 1
191 #define CLKMGR_NOCDIV_DIV4 2
192 #define CLKMGR_NOCDIV_DIV8 3
193 #define CLKMGR_CSPDBGCLK_DIV1 0
194 #define CLKMGR_CSPDBGCLK_DIV4 1
196 #define CLKMGR_MSCNT_CONST 200
197 #define CLKMGR_MDIV_CONST 6
198 #define CLKMGR_HSCNT_CONST 9
200 #define CLKMGR_VCOCALIB_MSCNT_MASK 0xff
201 #define CLKMGR_VCOCALIB_MSCNT_OFFSET 9
202 #define CLKMGR_VCOCALIB_HSCNT_MASK 0xff
204 #define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26
205 #define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27
206 #define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28
208 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
210 #endif /* _CLOCK_MANAGER_S10_ */