arch/arm/mach-socfpga/firewall.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <asm/io.h>
   8 #include <common.h>
   9 #include <asm/arch/firewall.h>
  10 #include <asm/arch/system_manager.h>
  11
  12 static void firewall_l4_per_disable(void)
  13 {
  14         const struct socfpga_firwall_l4_per *firwall_l4_per_base =
  15                 (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
  16         u32 i;
  17         const u32 *addr[] = {
  18                         &firwall_l4_per_base->nand,
  19                         &firwall_l4_per_base->nand_data,
  20                         &firwall_l4_per_base->usb0,
  21                         &firwall_l4_per_base->usb1,
  22                         &firwall_l4_per_base->spim0,
  23                         &firwall_l4_per_base->spim1,
  24                         &firwall_l4_per_base->emac0,
  25                         &firwall_l4_per_base->emac1,
  26                         &firwall_l4_per_base->emac2,
  27                         &firwall_l4_per_base->sdmmc,
  28                         &firwall_l4_per_base->gpio0,
  29                         &firwall_l4_per_base->gpio1,
  30                         &firwall_l4_per_base->i2c0,
  31                         &firwall_l4_per_base->i2c1,
  32                         &firwall_l4_per_base->i2c2,
  33                         &firwall_l4_per_base->i2c3,
  34                         &firwall_l4_per_base->i2c4,
  35                         &firwall_l4_per_base->timer0,
  36                         &firwall_l4_per_base->timer1,
  37                         &firwall_l4_per_base->uart0,
  38                         &firwall_l4_per_base->uart1
  39                         };
  40
  41         /*
  42          * The following lines of code will enable non-secure access
  43          * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
  44          * is needed as most OS run in non-secure mode. Thus we need to
  45          * enable non-secure access to these peripherals in order for the
  46          * OS to use these peripherals.
  47          */
  48         for (i = 0; i < ARRAY_SIZE(addr); i++)
  49                 writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
  50 }
  51
  52 static void firewall_l4_sys_disable(void)
  53 {
  54         const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
  55                 (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
  56         u32 i;
  57         const u32 *addr[] = {
  58                         &firwall_l4_sys_base->dma_ecc,
  59                         &firwall_l4_sys_base->emac0rx_ecc,
  60                         &firwall_l4_sys_base->emac0tx_ecc,
  61                         &firwall_l4_sys_base->emac1rx_ecc,
  62                         &firwall_l4_sys_base->emac1tx_ecc,
  63                         &firwall_l4_sys_base->emac2rx_ecc,
  64                         &firwall_l4_sys_base->emac2tx_ecc,
  65                         &firwall_l4_sys_base->nand_ecc,
  66                         &firwall_l4_sys_base->nand_read_ecc,
  67                         &firwall_l4_sys_base->nand_write_ecc,
  68                         &firwall_l4_sys_base->ocram_ecc,
  69                         &firwall_l4_sys_base->sdmmc_ecc,
  70                         &firwall_l4_sys_base->usb0_ecc,
  71                         &firwall_l4_sys_base->usb1_ecc,
  72                         &firwall_l4_sys_base->clock_manager,
  73                         &firwall_l4_sys_base->io_manager,
  74                         &firwall_l4_sys_base->reset_manager,
  75                         &firwall_l4_sys_base->system_manager,
  76                         &firwall_l4_sys_base->watchdog0,
  77                         &firwall_l4_sys_base->watchdog1,
  78                         &firwall_l4_sys_base->watchdog2,
  79                         &firwall_l4_sys_base->watchdog3
  80                 };
  81
  82         for (i = 0; i < ARRAY_SIZE(addr); i++)
  83                 writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
  84 }
  85
  86 static void firewall_bridge_disable(void)
  87 {
  88         /* disable lwsocf2fpga and soc2fpga bridge security */
  89         writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
  90         writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
  91 }
  92
  93 void firewall_setup(void)
  94 {
  95         firewall_l4_per_disable();
  96         firewall_l4_sys_disable();
  97         firewall_bridge_disable();
  98
  99         /* disable SMMU security */
 100         writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
 101
 102         /* enable non-secure interface to DMA330 DMA and peripherals */
 103         writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
 104                socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);
 105         writel(SYSMGR_DMAPERIPH_ALL_NS,
 106                socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);
 107 }