arch/arm/mach-socfpga/clock_manager_agilex.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <clk.h>
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <asm/arch/clock_manager.h>
  11 #include <asm/arch/system_manager.h>
  12 #include <asm/io.h>
  13 #include <dt-bindings/clock/agilex-clock.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 static ulong cm_get_rate_dm(u32 id)
  18 {
  19         struct udevice *dev;
  20         struct clk clk;
  21         ulong rate;
  22         int ret;
  23
  24         ret = uclass_get_device_by_driver(UCLASS_CLK,
  25                                           DM_GET_DRIVER(socfpga_agilex_clk),
  26                                           &dev);
  27         if (ret)
  28                 return 0;
  29
  30         clk.id = id;
  31         ret = clk_request(dev, &clk);
  32         if (ret < 0)
  33                 return 0;
  34
  35         rate = clk_get_rate(&clk);
  36
  37         clk_free(&clk);
  38
  39         if ((rate == (unsigned long)-ENOSYS) ||
  40             (rate == (unsigned long)-ENXIO) ||
  41             (rate == (unsigned long)-EIO)) {
  42                 debug("%s id %u: clk_get_rate err: %ld\n",
  43                       __func__, id, rate);
  44                 return 0;
  45         }
  46
  47         return rate;
  48 }
  49
  50 static u32 cm_get_rate_dm_khz(u32 id)
  51 {
  52         return cm_get_rate_dm(id) / 1000;
  53 }
  54
  55 unsigned long cm_get_mpu_clk_hz(void)
  56 {
  57         return cm_get_rate_dm(AGILEX_MPU_CLK);
  58 }
  59
  60 unsigned int cm_get_l4_sys_free_clk_hz(void)
  61 {
  62         return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
  63 }
  64
  65 u32 cm_get_qspi_controller_clk_hz(void)
  66 {
  67         return readl(socfpga_get_sysmgr_addr() +
  68                      SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
  69 }
  70
  71 void cm_print_clock_quick_summary(void)
  72 {
  73         printf("MPU       %10d kHz\n",
  74                cm_get_rate_dm_khz(AGILEX_MPU_CLK));
  75         printf("L4 Main     %8d kHz\n",
  76                cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
  77         printf("L4 sys free %8d kHz\n",
  78                cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
  79         printf("L4 MP       %8d kHz\n",
  80                cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
  81         printf("L4 SP       %8d kHz\n",
  82                cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
  83         printf("SDMMC       %8d kHz\n",
  84                cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
  85 }