arch/arm/mach-socfpga/clock_manager.c

   1 /*
   2  *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <wait_bit.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock_manager.h>
  11
  12 DECLARE_GLOBAL_DATA_PTR;
  13
  14 static const struct socfpga_clock_manager *clock_manager_base =
  15         (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
  16
  17 void cm_wait_for_lock(u32 mask)
  18 {
  19         u32 inter_val;
  20         u32 retry = 0;
  21         do {
  22                 inter_val = readl(&clock_manager_base->inter) & mask;
  23                 if (inter_val == mask)
  24                         retry++;
  25                 else
  26                         retry = 0;
  27                 if (retry >= 10)
  28                         break;
  29         } while (1);
  30 }
  31
  32 /* function to poll in the fsm busy bit */
  33 int cm_wait_for_fsm(void)
  34 {
  35         return wait_for_bit(__func__, (const u32 *)&clock_manager_base->stat,
  36                             CLKMGR_STAT_BUSY, false, 20000, false);
  37 }
  38
  39 int set_cpu_clk_info(void)
  40 {
  41         /* Calculate the clock frequencies required for drivers */
  42         cm_get_l4_sp_clk_hz();
  43         cm_get_mmc_controller_clk_hz();
  44
  45         gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
  46         gd->bd->bi_dsp_freq = 0;
  47         gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
  48
  49         return 0;
  50 }
  51
  52 int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  53 {
  54         cm_print_clock_quick_summary();
  55         return 0;
  56 }
  57
  58 U_BOOT_CMD(
  59         clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
  60         "display clocks",
  61         ""
  62 );