arch/arm/mach-rockchip/rk3399/rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <spl_gpio.h>
   8 #include <asm/armv8/mmu.h>
   9 #include <asm/io.h>
  10 #include <asm/arch-rockchip/gpio.h>
  11 #include <asm/arch-rockchip/grf_rk3399.h>
  12 #include <asm/arch-rockchip/hardware.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 #define GRF_EMMCCORE_CON11 0xff77f02c
  17 #define GRF_BASE        0xff770000
  18
  19 static struct mm_region rk3399_mem_map[] = {
  20         {
  21                 .virt = 0x0UL,
  22                 .phys = 0x0UL,
  23                 .size = 0xf8000000UL,
  24                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  25                          PTE_BLOCK_INNER_SHARE
  26         }, {
  27                 .virt = 0xf8000000UL,
  28                 .phys = 0xf8000000UL,
  29                 .size = 0x08000000UL,
  30                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  31                          PTE_BLOCK_NON_SHARE |
  32                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  33         }, {
  34                 /* List terminator */
  35                 0,
  36         }
  37 };
  38
  39 struct mm_region *mem_map = rk3399_mem_map;
  40
  41 #ifdef CONFIG_SPL_BUILD
  42
  43 #define TIMER_END_COUNT_L       0x00
  44 #define TIMER_END_COUNT_H       0x04
  45 #define TIMER_INIT_COUNT_L      0x10
  46 #define TIMER_INIT_COUNT_H      0x14
  47 #define TIMER_CONTROL_REG       0x1c
  48
  49 #define TIMER_EN        0x1
  50 #define TIMER_FMODE     BIT(0)
  51 #define TIMER_RMODE     BIT(1)
  52
  53 void rockchip_stimer_init(void)
  54 {
  55         /* If Timer already enabled, don't re-init it */
  56         u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
  57
  58         if (reg & TIMER_EN)
  59                 return;
  60
  61         writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
  62         writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
  63         writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
  64         writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
  65         writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
  66                TIMER_CONTROL_REG);
  67 }
  68 #endif
  69
  70 int dram_init_banksize(void)
  71 {
  72         size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
  73
  74         /* Reserve 0x200000 for ATF bl31 */
  75         gd->bd->bi_dram[0].start = 0x200000;
  76         gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
  77
  78         return 0;
  79 }
  80
  81 int arch_cpu_init(void)
  82 {
  83
  84 #ifdef CONFIG_SPL_BUILD
  85         struct rk3399_pmusgrf_regs *sgrf;
  86         struct rk3399_grf_regs *grf;
  87
  88         /*
  89          * Disable DDR and SRAM security regions.
  90          *
  91          * As we are entered from the BootROM, the region from
  92          * 0x0 through 0xfffff (i.e. the first MB of memory) will
  93          * be protected. This will cause issues with the DW_MMC
  94          * driver, which tries to DMA from/to the stack (likely)
  95          * located in this range.
  96          */
  97         sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
  98         rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
  99         rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
 100
 101         /*  eMMC clock generator: disable the clock multipilier */
 102         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 103         rk_clrreg(&grf->emmccore_con[11], 0x0ff);
 104 #endif
 105
 106         return 0;
 107 }
 108
 109 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 110 void board_debug_uart_init(void)
 111 {
 112 #define GRF_BASE        0xff770000
 113 #define GPIO0_BASE      0xff720000
 114 #define PMUGRF_BASE     0xff320000
 115         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
 116 #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
 117         struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
 118         struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
 119 #endif
 120
 121 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
 122         /* Enable early UART0 on the RK3399 */
 123         rk_clrsetreg(&grf->gpio2c_iomux,
 124                      GRF_GPIO2C0_SEL_MASK,
 125                      GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
 126         rk_clrsetreg(&grf->gpio2c_iomux,
 127                      GRF_GPIO2C1_SEL_MASK,
 128                      GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
 129 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
 130         /* Enable early UART3 on the RK3399 */
 131         rk_clrsetreg(&grf->gpio3b_iomux,
 132                      GRF_GPIO3B6_SEL_MASK,
 133                      GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
 134         rk_clrsetreg(&grf->gpio3b_iomux,
 135                      GRF_GPIO3B7_SEL_MASK,
 136                      GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
 137 #else
 138 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
 139         rk_setreg(&grf->io_vsel, 1 << 0);
 140
 141         /*
 142          * Let's enable these power rails here, we are already running the SPI
 143          * Flash based code.
 144          */
 145         spl_gpio_output(gpio, GPIO(BANK_B, 2), 1);  /* PP1500_EN */
 146         spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
 147
 148         spl_gpio_output(gpio, GPIO(BANK_B, 4), 1);  /* PP3000_EN */
 149         spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
 150 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
 151
 152         /* Enable early UART2 channel C on the RK3399 */
 153         rk_clrsetreg(&grf->gpio4c_iomux,
 154                      GRF_GPIO4C3_SEL_MASK,
 155                      GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
 156         rk_clrsetreg(&grf->gpio4c_iomux,
 157                      GRF_GPIO4C4_SEL_MASK,
 158                      GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
 159         /* Set channel C as UART2 input */
 160         rk_clrsetreg(&grf->soc_con7,
 161                      GRF_UART_DBG_SEL_MASK,
 162                      GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
 163 #endif
 164 }
 165 #endif
 166
 167 #ifdef CONFIG_SPL_BUILD
 168 const char *spl_decode_boot_device(u32 boot_device)
 169 {
 170         int i;
 171         static const struct {
 172                 u32 boot_device;
 173                 const char *ofpath;
 174         } spl_boot_devices_tbl[] = {
 175                 { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
 176                 { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
 177                 { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
 178         };
 179
 180         for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
 181                 if (spl_boot_devices_tbl[i].boot_device == boot_device)
 182                         return spl_boot_devices_tbl[i].ofpath;
 183
 184         return NULL;
 185 }
 186
 187 void spl_perform_fixups(struct spl_image_info *spl_image)
 188 {
 189         void *blob = spl_image->fdt_addr;
 190         const char *boot_ofpath;
 191         int chosen;
 192
 193         /*
 194          * Inject the ofpath of the device the full U-Boot (or Linux in
 195          * Falcon-mode) was booted from into the FDT, if a FDT has been
 196          * loaded at the same time.
 197          */
 198         if (!blob)
 199                 return;
 200
 201         boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
 202         if (!boot_ofpath) {
 203                 pr_err("%s: could not map boot_device to ofpath\n", __func__);
 204                 return;
 205         }
 206
 207         chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
 208         if (chosen < 0) {
 209                 pr_err("%s: could not find/create '/chosen'\n", __func__);
 210                 return;
 211         }
 212         fdt_setprop_string(blob, chosen,
 213                            "u-boot,spl-boot-device", boot_ofpath);
 214 }
 215 #endif