arch/arm/mach-rockchip/rk3399/rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <spl_gpio.h>
   8 #include <asm/armv8/mmu.h>
   9 #include <asm/io.h>
  10 #include <asm/arch-rockchip/gpio.h>
  11 #include <asm/arch-rockchip/grf_rk3399.h>
  12 #include <asm/arch-rockchip/hardware.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 #define GRF_EMMCCORE_CON11 0xff77f02c
  17 #define GRF_BASE        0xff770000
  18
  19 static struct mm_region rk3399_mem_map[] = {
  20         {
  21                 .virt = 0x0UL,
  22                 .phys = 0x0UL,
  23                 .size = 0xf8000000UL,
  24                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  25                          PTE_BLOCK_INNER_SHARE
  26         }, {
  27                 .virt = 0xf8000000UL,
  28                 .phys = 0xf8000000UL,
  29                 .size = 0x08000000UL,
  30                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  31                          PTE_BLOCK_NON_SHARE |
  32                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  33         }, {
  34                 /* List terminator */
  35                 0,
  36         }
  37 };
  38
  39 struct mm_region *mem_map = rk3399_mem_map;
  40
  41 #ifdef CONFIG_SPL_BUILD
  42
  43 #define TIMER_END_COUNT_L       0x00
  44 #define TIMER_END_COUNT_H       0x04
  45 #define TIMER_INIT_COUNT_L      0x10
  46 #define TIMER_INIT_COUNT_H      0x14
  47 #define TIMER_CONTROL_REG       0x1c
  48
  49 #define TIMER_EN        0x1
  50 #define TIMER_FMODE     BIT(0)
  51 #define TIMER_RMODE     BIT(1)
  52
  53 void rockchip_stimer_init(void)
  54 {
  55         /* If Timer already enabled, don't re-init it */
  56         u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
  57
  58         if (reg & TIMER_EN)
  59                 return;
  60
  61         writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
  62         writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
  63         writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
  64         writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
  65         writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
  66                TIMER_CONTROL_REG);
  67 }
  68 #endif
  69
  70 int dram_init_banksize(void)
  71 {
  72         size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
  73
  74         /* Reserve 0x200000 for ATF bl31 */
  75         gd->bd->bi_dram[0].start = 0x200000;
  76         gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
  77
  78         return 0;
  79 }
  80
  81 int arch_cpu_init(void)
  82 {
  83         /* We do some SoC one time setting here. */
  84         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  85
  86         /* Emmc clock generator: disable the clock multipilier */
  87         rk_clrreg(&grf->emmccore_con[11], 0x0ff);
  88
  89         return 0;
  90 }
  91
  92 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  93 void board_debug_uart_init(void)
  94 {
  95 #define GRF_BASE        0xff770000
  96 #define GPIO0_BASE      0xff720000
  97 #define PMUGRF_BASE     0xff320000
  98         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  99 #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
 100         struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
 101         struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
 102 #endif
 103
 104 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
 105         /* Enable early UART0 on the RK3399 */
 106         rk_clrsetreg(&grf->gpio2c_iomux,
 107                      GRF_GPIO2C0_SEL_MASK,
 108                      GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
 109         rk_clrsetreg(&grf->gpio2c_iomux,
 110                      GRF_GPIO2C1_SEL_MASK,
 111                      GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
 112 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
 113         /* Enable early UART3 on the RK3399 */
 114         rk_clrsetreg(&grf->gpio3b_iomux,
 115                      GRF_GPIO3B6_SEL_MASK,
 116                      GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
 117         rk_clrsetreg(&grf->gpio3b_iomux,
 118                      GRF_GPIO3B7_SEL_MASK,
 119                      GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
 120 #else
 121 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
 122         rk_setreg(&grf->io_vsel, 1 << 0);
 123
 124         /*
 125          * Let's enable these power rails here, we are already running the SPI
 126          * Flash based code.
 127          */
 128         spl_gpio_output(gpio, GPIO(BANK_B, 2), 1);  /* PP1500_EN */
 129         spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
 130
 131         spl_gpio_output(gpio, GPIO(BANK_B, 4), 1);  /* PP3000_EN */
 132         spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
 133 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
 134
 135         /* Enable early UART2 channel C on the RK3399 */
 136         rk_clrsetreg(&grf->gpio4c_iomux,
 137                      GRF_GPIO4C3_SEL_MASK,
 138                      GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
 139         rk_clrsetreg(&grf->gpio4c_iomux,
 140                      GRF_GPIO4C4_SEL_MASK,
 141                      GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
 142         /* Set channel C as UART2 input */
 143         rk_clrsetreg(&grf->soc_con7,
 144                      GRF_UART_DBG_SEL_MASK,
 145                      GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
 146 #endif
 147 }
 148 #endif