arch/arm/mach-rockchip/rk3288/sdram_rk3288.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  * Copyright 2014 Rockchip Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0
   6  *
   7  * Adapted from coreboot.
   8  */
   9
  10 #include <common.h>
  11 #include <clk.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <ram.h>
  15 #include <regmap.h>
  16 #include <syscon.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/cru_rk3288.h>
  20 #include <asm/arch/ddr_rk3288.h>
  21 #include <asm/arch/grf_rk3288.h>
  22 #include <asm/arch/pmu_rk3288.h>
  23 #include <asm/arch/sdram.h>
  24 #include <linux/err.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 struct chan_info {
  29         struct rk3288_ddr_pctl *pctl;
  30         struct rk3288_ddr_publ *publ;
  31         struct rk3288_msch *msch;
  32 };
  33
  34 struct dram_info {
  35         struct chan_info chan[2];
  36         struct ram_info info;
  37         struct udevice *ddr_clk;
  38         struct rk3288_cru *cru;
  39         struct rk3288_grf *grf;
  40         struct rk3288_sgrf *sgrf;
  41         struct rk3288_pmu *pmu;
  42 };
  43
  44 #ifdef CONFIG_SPL_BUILD
  45 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  46 {
  47         int i;
  48
  49         for (i = 0; i < n / sizeof(u32); i++) {
  50                 writel(*src, dest);
  51                 src++;
  52                 dest++;
  53         }
  54 }
  55
  56 static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
  57 {
  58         u32 phy_ctl_srstn_shift = 4 + 5 * ch;
  59         u32 ctl_psrstn_shift = 3 + 5 * ch;
  60         u32 ctl_srstn_shift = 2 + 5 * ch;
  61         u32 phy_psrstn_shift = 1 + 5 * ch;
  62         u32 phy_srstn_shift = 5 * ch;
  63
  64         rk_clrsetreg(&cru->cru_softrst_con[10],
  65                      1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
  66                      1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
  67                      1 << phy_srstn_shift,
  68                      phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
  69                      ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
  70                      phy << phy_srstn_shift);
  71 }
  72
  73 static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
  74 {
  75         u32 phy_ctl_srstn_shift = 4 + 5 * ch;
  76
  77         rk_clrsetreg(&cru->cru_softrst_con[10],
  78                      1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
  79 }
  80
  81 static void phy_pctrl_reset(struct rk3288_cru *cru,
  82                             struct rk3288_ddr_publ *publ,
  83                             u32 channel)
  84 {
  85         int i;
  86
  87         ddr_reset(cru, channel, 1, 1);
  88         udelay(1);
  89         clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
  90         for (i = 0; i < 4; i++)
  91                 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
  92
  93         udelay(10);
  94         setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
  95         for (i = 0; i < 4; i++)
  96                 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
  97
  98         udelay(10);
  99         ddr_reset(cru, channel, 1, 0);
 100         udelay(10);
 101         ddr_reset(cru, channel, 0, 0);
 102         udelay(10);
 103 }
 104
 105 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
 106         u32 freq)
 107 {
 108         int i;
 109         if (freq <= 250000000) {
 110                 if (freq <= 150000000)
 111                         clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 112                 else
 113                         setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 114                 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
 115                 for (i = 0; i < 4; i++)
 116                         setbits_le32(&publ->datx8[i].dxdllcr,
 117                                      DXDLLCR_DLLDIS);
 118
 119                 setbits_le32(&publ->pir, PIR_DLLBYP);
 120         } else {
 121                 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 122                 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
 123                 for (i = 0; i < 4; i++) {
 124                         clrbits_le32(&publ->datx8[i].dxdllcr,
 125                                      DXDLLCR_DLLDIS);
 126                 }
 127
 128                 clrbits_le32(&publ->pir, PIR_DLLBYP);
 129         }
 130 }
 131
 132 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
 133 {
 134         writel(DFI_INIT_START, &pctl->dfistcfg0);
 135         writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
 136                &pctl->dfistcfg1);
 137         writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
 138         writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
 139                &pctl->dfilpcfg0);
 140
 141         writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
 142         writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
 143         writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
 144         writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
 145         writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
 146         writel(1, &pctl->dfitphyupdtype0);
 147
 148         /* cs0 and cs1 write odt enable */
 149         writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
 150                &pctl->dfiodtcfg);
 151         /* odt write length */
 152         writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
 153         /* phyupd and ctrlupd disabled */
 154         writel(0, &pctl->dfiupdcfg);
 155 }
 156
 157 static void ddr_set_enable(struct rk3288_grf *grf, uint channel, bool enable)
 158 {
 159         uint val = 0;
 160
 161         if (enable) {
 162                 val = 1 << (channel ? DDR1_16BIT_EN_SHIFT :
 163                                 DDR0_16BIT_EN_SHIFT);
 164         }
 165         rk_clrsetreg(&grf->soc_con0,
 166                      1 << (channel ? DDR1_16BIT_EN_SHIFT : DDR0_16BIT_EN_SHIFT),
 167                      val);
 168 }
 169
 170 static void ddr_set_ddr3_mode(struct rk3288_grf *grf, uint channel,
 171                               bool ddr3_mode)
 172 {
 173         uint mask, val;
 174
 175         mask = 1 << (channel ? MSCH1_MAINDDR3_SHIFT : MSCH0_MAINDDR3_SHIFT);
 176         val = ddr3_mode << (channel ? MSCH1_MAINDDR3_SHIFT :
 177                                         MSCH0_MAINDDR3_SHIFT);
 178         rk_clrsetreg(&grf->soc_con0, mask, val);
 179 }
 180
 181 static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel,
 182                                bool enable, bool enable_bst, bool enable_odt)
 183 {
 184         uint mask;
 185         bool disable_bst = !enable_bst;
 186
 187         mask = channel ?
 188                 (1 << LPDDR3_EN1_SHIFT | 1 << UPCTL1_BST_DIABLE_SHIFT |
 189                         1 << UPCTL1_LPDDR3_ODT_EN_SHIFT) :
 190                 (1 << LPDDR3_EN0_SHIFT | 1 << UPCTL0_BST_DIABLE_SHIFT |
 191                         1 << UPCTL0_LPDDR3_ODT_EN_SHIFT);
 192         rk_clrsetreg(&grf->soc_con2, mask,
 193                      enable << (channel ? LPDDR3_EN1_SHIFT : LPDDR3_EN0_SHIFT) |
 194                      disable_bst << (channel ? UPCTL1_BST_DIABLE_SHIFT :
 195                                 UPCTL0_BST_DIABLE_SHIFT) |
 196                      enable_odt << (channel ? UPCTL1_LPDDR3_ODT_EN_SHIFT :
 197                                 UPCTL0_LPDDR3_ODT_EN_SHIFT));
 198 }
 199
 200 static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
 201                      const struct rk3288_sdram_params *sdram_params,
 202                      struct rk3288_grf *grf)
 203 {
 204         unsigned int burstlen;
 205
 206         burstlen = (sdram_params->base.noc_timing >> 18) & 0x7;
 207         copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
 208                     sizeof(sdram_params->pctl_timing));
 209         switch (sdram_params->base.dramtype) {
 210         case LPDDR3:
 211                 writel(sdram_params->pctl_timing.tcl - 1,
 212                        &pctl->dfitrddataen);
 213                 writel(sdram_params->pctl_timing.tcwl,
 214                        &pctl->dfitphywrlat);
 215                 burstlen >>= 1;
 216                 writel(LPDDR2_S4 | 0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT |
 217                        LPDDR2_EN | burstlen << BURSTLENGTH_SHIFT |
 218                        (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST |
 219                        1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
 220                        &pctl->mcfg);
 221                 ddr_set_ddr3_mode(grf, channel, false);
 222                 ddr_set_enable(grf, channel, true);
 223                 ddr_set_en_bst_odt(grf, channel, true, false,
 224                                    sdram_params->base.odt);
 225                 break;
 226         case DDR3:
 227                 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
 228                         writel(sdram_params->pctl_timing.tcl - 3,
 229                                &pctl->dfitrddataen);
 230                 } else {
 231                         writel(sdram_params->pctl_timing.tcl - 2,
 232                                &pctl->dfitrddataen);
 233                 }
 234                 writel(sdram_params->pctl_timing.tcwl - 1,
 235                        &pctl->dfitphywrlat);
 236                 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
 237                        DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
 238                        1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
 239                        &pctl->mcfg);
 240                 ddr_set_ddr3_mode(grf, channel, true);
 241                 ddr_set_enable(grf, channel, true);
 242
 243                 ddr_set_en_bst_odt(grf, channel, false, true, false);
 244                 break;
 245         }
 246
 247         setbits_le32(&pctl->scfg, 1);
 248 }
 249
 250 static void phy_cfg(const struct chan_info *chan, u32 channel,
 251                     const struct rk3288_sdram_params *sdram_params)
 252 {
 253         struct rk3288_ddr_publ *publ = chan->publ;
 254         struct rk3288_msch *msch = chan->msch;
 255         uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
 256         u32 dinit2, tmp;
 257         int i;
 258
 259         dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
 260         /* DDR PHY Timing */
 261         copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
 262                     sizeof(sdram_params->phy_timing));
 263         writel(sdram_params->base.noc_timing, &msch->ddrtiming);
 264         writel(0x3f, &msch->readlatency);
 265         writel(sdram_params->base.noc_activate, &msch->activate);
 266         writel(2 << BUSWRTORD_SHIFT | 2 << BUSRDTOWR_SHIFT |
 267                1 << BUSRDTORD_SHIFT, &msch->devtodev);
 268         writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
 269                DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
 270                8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
 271         writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
 272                DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
 273                &publ->ptr[1]);
 274         writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
 275                DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
 276                &publ->ptr[2]);
 277
 278         switch (sdram_params->base.dramtype) {
 279         case LPDDR3:
 280                 clrsetbits_le32(&publ->pgcr, 0x1F,
 281                                 0 << PGCR_DFTLMT_SHIFT |
 282                                 0 << PGCR_DFTCMP_SHIFT |
 283                                 1 << PGCR_DQSCFG_SHIFT |
 284                                 0 << PGCR_ITMDMD_SHIFT);
 285                 /* DDRMODE select LPDDR3 */
 286                 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
 287                                 DDRMD_LPDDR2_LPDDR3 << DDRMD_SHIFT);
 288                 clrsetbits_le32(&publ->dxccr,
 289                                 DQSNRES_MASK << DQSNRES_SHIFT |
 290                                 DQSRES_MASK << DQSRES_SHIFT,
 291                                 4 << DQSRES_SHIFT | 0xc << DQSNRES_SHIFT);
 292                 tmp = readl(&publ->dtpr[1]);
 293                 tmp = ((tmp >> TDQSCKMAX_SHIFT) & TDQSCKMAX_MASK) -
 294                         ((tmp >> TDQSCK_SHIFT) & TDQSCK_MASK);
 295                 clrsetbits_le32(&publ->dsgcr,
 296                                 DQSGE_MASK << DQSGE_SHIFT |
 297                                 DQSGX_MASK << DQSGX_SHIFT,
 298                                 tmp << DQSGE_SHIFT | tmp << DQSGX_SHIFT);
 299                 break;
 300         case DDR3:
 301                 clrbits_le32(&publ->pgcr, 0x1f);
 302                 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
 303                                 DDRMD_DDR3 << DDRMD_SHIFT);
 304                 break;
 305         }
 306         if (sdram_params->base.odt) {
 307                 /*dynamic RTT enable */
 308                 for (i = 0; i < 4; i++)
 309                         setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
 310         } else {
 311                 /*dynamic RTT disable */
 312                 for (i = 0; i < 4; i++)
 313                         clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
 314         }
 315 }
 316
 317 static void phy_init(struct rk3288_ddr_publ *publ)
 318 {
 319         setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
 320                 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
 321         udelay(1);
 322         while ((readl(&publ->pgsr) &
 323                 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
 324                 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
 325                 ;
 326 }
 327
 328 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
 329                          u32 cmd, u32 arg)
 330 {
 331         writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
 332         udelay(1);
 333         while (readl(&pctl->mcmd) & START_CMD)
 334                 ;
 335 }
 336
 337 static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
 338                                    u32 rank, u32 cmd, u32 ma, u32 op)
 339 {
 340         send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
 341                      (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
 342 }
 343
 344 static void memory_init(struct rk3288_ddr_publ *publ,
 345                         u32 dramtype)
 346 {
 347         setbits_le32(&publ->pir,
 348                      (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
 349                       | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
 350                       | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
 351         udelay(1);
 352         while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
 353                 != (PGSR_IDONE | PGSR_DLDONE))
 354                 ;
 355 }
 356
 357 static void move_to_config_state(struct rk3288_ddr_publ *publ,
 358                                  struct rk3288_ddr_pctl *pctl)
 359 {
 360         unsigned int state;
 361
 362         while (1) {
 363                 state = readl(&pctl->stat) & PCTL_STAT_MSK;
 364
 365                 switch (state) {
 366                 case LOW_POWER:
 367                         writel(WAKEUP_STATE, &pctl->sctl);
 368                         while ((readl(&pctl->stat) & PCTL_STAT_MSK)
 369                                 != ACCESS)
 370                                 ;
 371                         /* wait DLL lock */
 372                         while ((readl(&publ->pgsr) & PGSR_DLDONE)
 373                                 != PGSR_DLDONE)
 374                                 ;
 375                         /* if at low power state,need wakeup first,
 376                          * and then enter the config
 377                          * so here no break.
 378                          */
 379                 case ACCESS:
 380                         /* no break */
 381                 case INIT_MEM:
 382                         writel(CFG_STATE, &pctl->sctl);
 383                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
 384                                 ;
 385                         break;
 386                 case CONFIG:
 387                         return;
 388                 default:
 389                         break;
 390                 }
 391         }
 392 }
 393
 394 static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel,
 395                                 u32 n, struct rk3288_grf *grf)
 396 {
 397         struct rk3288_ddr_pctl *pctl = chan->pctl;
 398         struct rk3288_ddr_publ *publ = chan->publ;
 399         struct rk3288_msch *msch = chan->msch;
 400
 401         if (n == 1) {
 402                 setbits_le32(&pctl->ppcfg, 1);
 403                 writel(RK_SETBITS(1 << (8 + channel)), &grf->soc_con0);
 404                 setbits_le32(&msch->ddrtiming, 1 << 31);
 405                 /* Data Byte disable*/
 406                 clrbits_le32(&publ->datx8[2].dxgcr, 1);
 407                 clrbits_le32(&publ->datx8[3].dxgcr, 1);
 408                 /*disable DLL */
 409                 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
 410                 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
 411         } else {
 412                 clrbits_le32(&pctl->ppcfg, 1);
 413                 writel(RK_CLRBITS(1 << (8 + channel)), &grf->soc_con0);
 414                 clrbits_le32(&msch->ddrtiming, 1 << 31);
 415                 /* Data Byte enable*/
 416                 setbits_le32(&publ->datx8[2].dxgcr, 1);
 417                 setbits_le32(&publ->datx8[3].dxgcr, 1);
 418
 419                 /*enable DLL */
 420                 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
 421                 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
 422                 /* reset DLL */
 423                 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
 424                 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
 425                 udelay(10);
 426                 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
 427                 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
 428         }
 429         setbits_le32(&pctl->dfistcfg0, 1 << 2);
 430 }
 431
 432 static int data_training(const struct chan_info *chan, u32 channel,
 433                          const struct rk3288_sdram_params *sdram_params)
 434 {
 435         unsigned int j;
 436         int ret = 0;
 437         u32 rank;
 438         int i;
 439         u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
 440         struct rk3288_ddr_publ *publ = chan->publ;
 441         struct rk3288_ddr_pctl *pctl = chan->pctl;
 442
 443         /* disable auto refresh */
 444         writel(0, &pctl->trefi);
 445
 446         if (sdram_params->base.dramtype != LPDDR3)
 447                 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
 448         rank = sdram_params->ch[channel].rank | 1;
 449         for (j = 0; j < ARRAY_SIZE(step); j++) {
 450                 /*
 451                  * trigger QSTRN and RVTRN
 452                  * clear DTDONE status
 453                  */
 454                 setbits_le32(&publ->pir, PIR_CLRSR);
 455
 456                 /* trigger DTT */
 457                 setbits_le32(&publ->pir,
 458                              PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
 459                              PIR_CLRSR);
 460                 udelay(1);
 461                 /* wait echo byte DTDONE */
 462                 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
 463                         != rank)
 464                         ;
 465                 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
 466                         != rank)
 467                         ;
 468                 if (!(readl(&pctl->ppcfg) & 1)) {
 469                         while ((readl(&publ->datx8[2].dxgsr[0])
 470                                 & rank) != rank)
 471                                 ;
 472                         while ((readl(&publ->datx8[3].dxgsr[0])
 473                                 & rank) != rank)
 474                                 ;
 475                 }
 476                 if (readl(&publ->pgsr) &
 477                     (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
 478                         ret = -1;
 479                         break;
 480                 }
 481         }
 482         /* send some auto refresh to complement the lost while DTT */
 483         for (i = 0; i < (rank > 1 ? 8 : 4); i++)
 484                 send_command(pctl, rank, REF_CMD, 0);
 485
 486         if (sdram_params->base.dramtype != LPDDR3)
 487                 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
 488
 489         /* resume auto refresh */
 490         writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
 491
 492         return ret;
 493 }
 494
 495 static void move_to_access_state(const struct chan_info *chan)
 496 {
 497         struct rk3288_ddr_publ *publ = chan->publ;
 498         struct rk3288_ddr_pctl *pctl = chan->pctl;
 499         unsigned int state;
 500
 501         while (1) {
 502                 state = readl(&pctl->stat) & PCTL_STAT_MSK;
 503
 504                 switch (state) {
 505                 case LOW_POWER:
 506                         if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
 507                                         LP_TRIG_MASK) == 1)
 508                                 return;
 509
 510                         writel(WAKEUP_STATE, &pctl->sctl);
 511                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
 512                                 ;
 513                         /* wait DLL lock */
 514                         while ((readl(&publ->pgsr) & PGSR_DLDONE)
 515                                 != PGSR_DLDONE)
 516                                 ;
 517                         break;
 518                 case INIT_MEM:
 519                         writel(CFG_STATE, &pctl->sctl);
 520                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
 521                                 ;
 522                 case CONFIG:
 523                         writel(GO_STATE, &pctl->sctl);
 524                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
 525                                 ;
 526                         break;
 527                 case ACCESS:
 528                         return;
 529                 default:
 530                         break;
 531                 }
 532         }
 533 }
 534
 535 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
 536                          const struct rk3288_sdram_params *sdram_params)
 537 {
 538         struct rk3288_ddr_publ *publ = chan->publ;
 539
 540         if (sdram_params->ch[chnum].bk == 3)
 541                 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
 542                                 1 << PDQ_SHIFT);
 543         else
 544                 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
 545
 546         writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
 547 }
 548
 549 static void dram_all_config(const struct dram_info *dram,
 550                             const struct rk3288_sdram_params *sdram_params)
 551 {
 552         unsigned int chan;
 553         u32 sys_reg = 0;
 554
 555         sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
 556         sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
 557         for (chan = 0; chan < sdram_params->num_channels; chan++) {
 558                 const struct rk3288_sdram_channel *info =
 559                         &sdram_params->ch[chan];
 560
 561                 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
 562                 sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
 563                 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
 564                 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
 565                 sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
 566                 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
 567                 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
 568                 sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
 569                 sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
 570
 571                 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
 572         }
 573         writel(sys_reg, &dram->pmu->sys_reg[2]);
 574         writel(RK_CLRSETBITS(0x1F, sdram_params->base.stride),
 575                &dram->sgrf->soc_con2);
 576 }
 577
 578 static int sdram_init(const struct dram_info *dram,
 579                       const struct rk3288_sdram_params *sdram_params)
 580 {
 581         int channel;
 582         int zqcr;
 583         int ret;
 584
 585         debug("%s start\n", __func__);
 586         if ((sdram_params->base.dramtype == DDR3 &&
 587              sdram_params->base.ddr_freq > 800000000) ||
 588             (sdram_params->base.dramtype == LPDDR3 &&
 589              sdram_params->base.ddr_freq > 533000000)) {
 590                 debug("SDRAM frequency is too high!");
 591                 return -E2BIG;
 592         }
 593
 594         debug("ddr clk %s\n", dram->ddr_clk->name);
 595         ret = clk_set_rate(dram->ddr_clk, sdram_params->base.ddr_freq);
 596         debug("ret=%d\n", ret);
 597         if (ret) {
 598                 debug("Could not set DDR clock\n");
 599                 return ret;
 600         }
 601
 602         for (channel = 0; channel < 2; channel++) {
 603                 const struct chan_info *chan = &dram->chan[channel];
 604                 struct rk3288_ddr_pctl *pctl = chan->pctl;
 605                 struct rk3288_ddr_publ *publ = chan->publ;
 606
 607                 phy_pctrl_reset(dram->cru, publ, channel);
 608                 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
 609
 610                 if (channel >= sdram_params->num_channels)
 611                         continue;
 612
 613                 dfi_cfg(pctl, sdram_params->base.dramtype);
 614
 615                 pctl_cfg(channel, pctl, sdram_params, dram->grf);
 616
 617                 phy_cfg(chan, channel, sdram_params);
 618
 619                 phy_init(publ);
 620
 621                 writel(POWER_UP_START, &pctl->powctl);
 622                 while (!(readl(&pctl->powstat) & POWER_UP_DONE))
 623                         ;
 624
 625                 memory_init(publ, sdram_params->base.dramtype);
 626                 move_to_config_state(publ, pctl);
 627
 628                 if (sdram_params->base.dramtype == LPDDR3) {
 629                         send_command(pctl, 3, DESELECT_CMD, 0);
 630                         udelay(1);
 631                         send_command(pctl, 3, PREA_CMD, 0);
 632                         udelay(1);
 633                         send_command_op(pctl, 3, MRS_CMD, 63, 0xfc);
 634                         udelay(1);
 635                         send_command_op(pctl, 3, MRS_CMD, 1,
 636                                         sdram_params->phy_timing.mr[1]);
 637                         udelay(1);
 638                         send_command_op(pctl, 3, MRS_CMD, 2,
 639                                         sdram_params->phy_timing.mr[2]);
 640                         udelay(1);
 641                         send_command_op(pctl, 3, MRS_CMD, 3,
 642                                         sdram_params->phy_timing.mr[3]);
 643                         udelay(1);
 644                 }
 645
 646                 set_bandwidth_ratio(chan, channel,
 647                                     sdram_params->ch[channel].bw, dram->grf);
 648                 /*
 649                  * set cs
 650                  * CS0, n=1
 651                  * CS1, n=2
 652                  * CS0 & CS1, n = 3
 653                  */
 654                 clrsetbits_le32(&publ->pgcr, 0xF << 18,
 655                                 (sdram_params->ch[channel].rank | 1) << 18);
 656                 /* DS=40ohm,ODT=155ohm */
 657                 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
 658                         2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
 659                         0x19 << PD_OUTPUT_SHIFT;
 660                 writel(zqcr, &publ->zq1cr[0]);
 661                 writel(zqcr, &publ->zq0cr[0]);
 662
 663                 if (sdram_params->base.dramtype == LPDDR3) {
 664                         /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
 665                         udelay(10);
 666                         send_command_op(pctl,
 667                                         sdram_params->ch[channel].rank | 1,
 668                                         MRS_CMD, 11,
 669                                         sdram_params->base.odt ? 3 : 0);
 670                         if (channel == 0) {
 671                                 writel(0, &pctl->mrrcfg0);
 672                                 send_command_op(pctl, 1, MRR_CMD, 8, 0);
 673                                 /* S8 */
 674                                 if ((readl(&pctl->mrrstat0) & 0x3) != 3) {
 675                                         debug("failed!");
 676                                         return -EREMOTEIO;
 677                                 }
 678                         }
 679                 }
 680
 681                 if (-1 == data_training(chan, channel, sdram_params)) {
 682                         if (sdram_params->base.dramtype == LPDDR3) {
 683                                 ddr_phy_ctl_reset(dram->cru, channel, 1);
 684                                 udelay(10);
 685                                 ddr_phy_ctl_reset(dram->cru, channel, 0);
 686                                 udelay(10);
 687                         }
 688                         debug("failed!");
 689                         return -EIO;
 690                 }
 691
 692                 if (sdram_params->base.dramtype == LPDDR3) {
 693                         u32 i;
 694                         writel(0, &pctl->mrrcfg0);
 695                         for (i = 0; i < 17; i++)
 696                                 send_command_op(pctl, 1, MRR_CMD, i, 0);
 697                 }
 698                 move_to_access_state(chan);
 699         }
 700         dram_all_config(dram, sdram_params);
 701         debug("%s done\n", __func__);
 702
 703         return 0;
 704 }
 705 #endif
 706
 707 size_t sdram_size_mb(struct rk3288_pmu *pmu)
 708 {
 709         u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
 710         size_t chipsize_mb = 0;
 711         size_t size_mb = 0;
 712         u32 ch;
 713         u32 sys_reg = readl(&pmu->sys_reg[2]);
 714         u32 chans;
 715
 716         chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
 717
 718         for (ch = 0; ch < chans; ch++) {
 719                 rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
 720                         SYS_REG_RANK_MASK);
 721                 col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
 722                 bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
 723                 cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
 724                                 SYS_REG_CS0_ROW_MASK);
 725                 cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
 726                                 SYS_REG_CS1_ROW_MASK);
 727                 bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
 728                         SYS_REG_BW_MASK;
 729                 row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 730                         SYS_REG_ROW_3_4_MASK;
 731
 732                 chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
 733
 734                 if (rank > 1)
 735                         chipsize_mb += chipsize_mb >>
 736                                 (cs0_row - cs1_row);
 737                 if (row_3_4)
 738                         chipsize_mb = chipsize_mb * 3 / 4;
 739                 size_mb += chipsize_mb;
 740         }
 741
 742         /*
 743         * we use the 0x00000000~0xfeffffff space since 0xff000000~0xffffffff
 744         * is SoC register space (i.e. reserved)
 745         */
 746         size_mb = min(size_mb, 0xff000000 >> 20);
 747
 748         return size_mb;
 749 }
 750
 751 #ifdef CONFIG_SPL_BUILD
 752 static int setup_sdram(struct udevice *dev)
 753 {
 754         struct dram_info *priv = dev_get_priv(dev);
 755         struct rk3288_sdram_params params;
 756         const void *blob = gd->fdt_blob;
 757         int node = dev->of_offset;
 758         int i, ret;
 759
 760         params.num_channels = fdtdec_get_int(blob, node,
 761                                              "rockchip,num-channels", 1);
 762         for (i = 0; i < params.num_channels; i++) {
 763                 ret = fdtdec_get_byte_array(blob, node,
 764                                             "rockchip,sdram-channel",
 765                                             (u8 *)&params.ch[i],
 766                                             sizeof(params.ch[i]));
 767                 if (ret) {
 768                         debug("%s: Cannot read rockchip,sdram-channel\n",
 769                               __func__);
 770                         return -EINVAL;
 771                 }
 772         }
 773         ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
 774                                    (u32 *)&params.pctl_timing,
 775                                    sizeof(params.pctl_timing) / sizeof(u32));
 776         if (ret) {
 777                 debug("%s: Cannot read rockchip,pctl-timing\n", __func__);
 778                 return -EINVAL;
 779         }
 780         ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
 781                                    (u32 *)&params.phy_timing,
 782                                    sizeof(params.phy_timing) / sizeof(u32));
 783         if (ret) {
 784                 debug("%s: Cannot read rockchip,phy-timing\n", __func__);
 785                 return -EINVAL;
 786         }
 787         ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
 788                                    (u32 *)&params.base,
 789                                    sizeof(params.base) / sizeof(u32));
 790         if (ret) {
 791                 debug("%s: Cannot read rockchip,sdram-params\n", __func__);
 792                 return -EINVAL;
 793         }
 794
 795         return sdram_init(priv, &params);
 796 }
 797 #endif
 798
 799 static int rk3288_dmc_probe(struct udevice *dev)
 800 {
 801         struct dram_info *priv = dev_get_priv(dev);
 802         struct regmap *map;
 803         int ret;
 804
 805         map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
 806         if (IS_ERR(map))
 807                 return PTR_ERR(map);
 808         priv->chan[0].msch = regmap_get_range(map, 0);
 809         priv->chan[1].msch = (struct rk3288_msch *)
 810                         (regmap_get_range(map, 0) + 0x80);
 811
 812         map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
 813         if (IS_ERR(map))
 814                 return PTR_ERR(map);
 815         priv->grf = regmap_get_range(map, 0);
 816
 817         map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_SGRF);
 818         if (IS_ERR(map))
 819                 return PTR_ERR(map);
 820         priv->sgrf = regmap_get_range(map, 0);
 821
 822         map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_PMU);
 823         if (IS_ERR(map))
 824                 return PTR_ERR(map);
 825         priv->pmu = regmap_get_range(map, 0);
 826
 827         ret = regmap_init_mem(dev, &map);
 828         if (ret)
 829                 return ret;
 830         priv->chan[0].pctl = regmap_get_range(map, 0);
 831         priv->chan[0].publ = regmap_get_range(map, 1);
 832         priv->chan[1].pctl = regmap_get_range(map, 2);
 833         priv->chan[1].publ = regmap_get_range(map, 3);
 834
 835         ret = uclass_get_device(UCLASS_CLK, CLK_DDR, &priv->ddr_clk);
 836         if (ret)
 837                 return ret;
 838
 839         priv->cru = rockchip_get_cru();
 840         if (IS_ERR(priv->cru))
 841                 return PTR_ERR(priv->cru);
 842 #ifdef CONFIG_SPL_BUILD
 843         ret = setup_sdram(dev);
 844         if (ret)
 845                 return ret;
 846 #endif
 847         priv->info.base = 0;
 848         priv->info.size = sdram_size_mb(priv->pmu) << 20;
 849
 850         return 0;
 851 }
 852
 853 static int rk3288_dmc_get_info(struct udevice *dev, struct ram_info *info)
 854 {
 855         struct dram_info *priv = dev_get_priv(dev);
 856
 857         *info = priv->info;
 858
 859         return 0;
 860 }
 861
 862 static struct ram_ops rk3288_dmc_ops = {
 863         .get_info = rk3288_dmc_get_info,
 864 };
 865
 866 static const struct udevice_id rk3288_dmc_ids[] = {
 867         { .compatible = "rockchip,rk3288-dmc" },
 868         { }
 869 };
 870
 871 U_BOOT_DRIVER(dmc_rk3288) = {
 872         .name = "rk3288_dmc",
 873         .id = UCLASS_RAM,
 874         .of_match = rk3288_dmc_ids,
 875         .ops = &rk3288_dmc_ops,
 876         .probe = rk3288_dmc_probe,
 877         .priv_auto_alloc_size = sizeof(struct dram_info),
 878 };