1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
12 #include <asm/armv7.h>
14 #include <asm/arch-rockchip/bootrom.h>
15 #include <asm/arch-rockchip/clock.h>
16 #include <asm/arch-rockchip/cru.h>
17 #include <asm/arch-rockchip/hardware.h>
18 #include <asm/arch-rockchip/grf_rk3288.h>
19 #include <asm/arch-rockchip/pmu_rk3288.h>
20 #include <asm/arch-rockchip/qos_rk3288.h>
21 #include <asm/arch-rockchip/sdram.h>
22 #include <linux/err.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define GRF_BASE 0xff770000
28 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
29 [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
30 [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
33 #ifdef CONFIG_SPL_BUILD
34 static void configure_l2ctlr(void)
38 l2ctlr = read_l2ctlr();
39 l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
42 * Data RAM write latency: 2 cycles
43 * Data RAM read latency: 2 cycles
44 * Data RAM setup latency: 1 cycle
45 * Tag RAM write latency: 1 cycle
46 * Tag RAM read latency: 1 cycle
47 * Tag RAM setup latency: 1 cycle
49 l2ctlr |= (1 << 3 | 1 << 0);
54 int rk3288_qos_init(void)
56 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
57 /* set vop qos to higher priority */
58 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
59 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
61 if (!fdt_node_check_compatible(gd->fdt_blob, 0,
62 "rockchip,rk3288-tinker")) {
63 /* set isp qos to higher priority */
64 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
65 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
66 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
72 int arch_cpu_init(void)
74 #ifdef CONFIG_SPL_BUILD
77 /* We do some SoC one time setting here. */
78 struct rk3288_grf * const grf = (void *)GRF_BASE;
80 /* Use rkpwm by default */
81 rk_setreg(&grf->soc_con2, 1 << 0);
84 * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
87 rk_clrreg(&grf->soc_con0, 1 << 12);
95 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
96 void board_debug_uart_init(void)
98 /* Enable early UART on the RK3288 */
99 struct rk3288_grf * const grf = (void *)GRF_BASE;
101 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
102 GPIO7C6_MASK << GPIO7C6_SHIFT,
103 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
104 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
108 __weak int rk3288_board_late_init(void)
113 int rk_board_late_init(void)
115 return rk3288_board_late_init();
118 static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc,
121 static const struct {
128 { "cpll", CLK_CODEC },
129 { "gpll", CLK_GENERAL },
130 #ifdef CONFIG_ROCKCHIP_RK3036
139 ret = rockchip_get_clk(&dev);
141 printf("clk-uclass not found\n");
145 for (i = 0; i < ARRAY_SIZE(clks); i++) {
150 ret = clk_request(dev, &clk);
154 rate = clk_get_rate(&clk);
155 printf("%s: %lu\n", clks[i].name, rate);
164 clock, 2, 1, do_clock,
165 "display information about clocks",