arch/arm/mach-rockchip/rk3288/rk3288.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
   4  */
   5 #include <common.h>
   6 #include <dm.h>
   7 #include <env.h>
   8 #include <clk.h>
   9 #include <init.h>
  10 #include <asm/armv7.h>
  11 #include <asm/io.h>
  12 #include <asm/arch-rockchip/bootrom.h>
  13 #include <asm/arch-rockchip/clock.h>
  14 #include <asm/arch-rockchip/cru.h>
  15 #include <asm/arch-rockchip/hardware.h>
  16 #include <asm/arch-rockchip/grf_rk3288.h>
  17 #include <asm/arch-rockchip/pmu_rk3288.h>
  18 #include <asm/arch-rockchip/qos_rk3288.h>
  19 #include <asm/arch-rockchip/sdram.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #define GRF_BASE        0xff770000
  24
  25 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  26         [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
  27         [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
  28 };
  29
  30 #ifdef CONFIG_SPL_BUILD
  31 static void configure_l2ctlr(void)
  32 {
  33         u32 l2ctlr;
  34
  35         l2ctlr = read_l2ctlr();
  36         l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
  37
  38         /*
  39          * Data RAM write latency: 2 cycles
  40          * Data RAM read latency: 2 cycles
  41          * Data RAM setup latency: 1 cycle
  42          * Tag RAM write latency: 1 cycle
  43          * Tag RAM read latency: 1 cycle
  44          * Tag RAM setup latency: 1 cycle
  45          */
  46         l2ctlr |= (1 << 3 | 1 << 0);
  47         write_l2ctlr(l2ctlr);
  48 }
  49 #endif
  50
  51 int rk3288_qos_init(void)
  52 {
  53         int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
  54         /* set vop qos to higher priority */
  55         writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
  56         writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
  57
  58         if (!fdt_node_check_compatible(gd->fdt_blob, 0,
  59                                        "rockchip,rk3288-tinker")) {
  60                 /* set isp qos to higher priority */
  61                 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
  62                 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
  63                 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
  64         }
  65
  66         return 0;
  67 }
  68
  69 int arch_cpu_init(void)
  70 {
  71 #ifdef CONFIG_SPL_BUILD
  72         configure_l2ctlr();
  73 #else
  74         /* We do some SoC one time setting here. */
  75         struct rk3288_grf * const grf = (void *)GRF_BASE;
  76
  77         /* Use rkpwm by default */
  78         rk_setreg(&grf->soc_con2, 1 << 0);
  79
  80         /*
  81          * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
  82          * cleared
  83          */
  84         rk_clrreg(&grf->soc_con0, 1 << 12);
  85
  86         rk3288_qos_init();
  87 #endif
  88
  89         return 0;
  90 }
  91
  92 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  93 void board_debug_uart_init(void)
  94 {
  95         /* Enable early UART on the RK3288 */
  96         struct rk3288_grf * const grf = (void *)GRF_BASE;
  97
  98         rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
  99                      GPIO7C6_MASK << GPIO7C6_SHIFT,
 100                      GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
 101                      GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 102 }
 103 #endif
 104
 105 __weak int rk3288_board_late_init(void)
 106 {
 107         return 0;
 108 }
 109
 110 int rk_board_late_init(void)
 111 {
 112         return rk3288_board_late_init();
 113 }
 114
 115 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
 116                        char * const argv[])
 117 {
 118         static const struct {
 119                 char *name;
 120                 int id;
 121         } clks[] = {
 122                 { "osc", CLK_OSC },
 123                 { "apll", CLK_ARM },
 124                 { "dpll", CLK_DDR },
 125                 { "cpll", CLK_CODEC },
 126                 { "gpll", CLK_GENERAL },
 127 #ifdef CONFIG_ROCKCHIP_RK3036
 128                 { "mpll", CLK_NEW },
 129 #else
 130                 { "npll", CLK_NEW },
 131 #endif
 132         };
 133         int ret, i;
 134         struct udevice *dev;
 135
 136         ret = rockchip_get_clk(&dev);
 137         if (ret) {
 138                 printf("clk-uclass not found\n");
 139                 return 0;
 140         }
 141
 142         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 143                 struct clk clk;
 144                 ulong rate;
 145
 146                 clk.id = clks[i].id;
 147                 ret = clk_request(dev, &clk);
 148                 if (ret < 0)
 149                         continue;
 150
 151                 rate = clk_get_rate(&clk);
 152                 printf("%s: %lu\n", clks[i].name, rate);
 153
 154                 clk_free(&clk);
 155         }
 156
 157         return 0;
 158 }
 159
 160 U_BOOT_CMD(
 161         clock, 2, 1, do_clock,
 162         "display information about clocks",
 163         ""
 164 );