arch/arm/mach-omap2/omap5/hwinit.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *
   4  * Functions for omap5 based boards.
   5  *
   6  * (C) Copyright 2011
   7  * Texas Instruments, <www.ti.com>
   8  *
   9  * Author :
  10  *      Aneesh V        <aneesh@ti.com>
  11  *      Steve Sakoman   <steve@sakoman.com>
  12  *      Sricharan       <r.sricharan@ti.com>
  13  */
  14 #include <common.h>
  15 #include <cpu_func.h>
  16 #include <palmas.h>
  17 #include <asm/armv7.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/clock.h>
  21 #include <linux/sizes.h>
  22 #include <asm/utils.h>
  23 #include <asm/arch/gpio.h>
  24 #include <asm/emif.h>
  25 #include <asm/omap_common.h>
  26
  27 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  28
  29 #if !CONFIG_IS_ENABLED(DM_GPIO)
  30 static struct gpio_bank gpio_bank_54xx[8] = {
  31         { (void *)OMAP54XX_GPIO1_BASE },
  32         { (void *)OMAP54XX_GPIO2_BASE },
  33         { (void *)OMAP54XX_GPIO3_BASE },
  34         { (void *)OMAP54XX_GPIO4_BASE },
  35         { (void *)OMAP54XX_GPIO5_BASE },
  36         { (void *)OMAP54XX_GPIO6_BASE },
  37         { (void *)OMAP54XX_GPIO7_BASE },
  38         { (void *)OMAP54XX_GPIO8_BASE },
  39 };
  40
  41 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  42 #endif
  43
  44 void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
  45 {
  46         int i;
  47         struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
  48
  49         for (i = 0; i < size; i++, pad++)
  50                 writel(pad->val, base + pad->offset);
  51 }
  52
  53 #ifdef CONFIG_SPL_BUILD
  54 /* LPDDR2 specific IO settings */
  55 static void io_settings_lpddr2(void)
  56 {
  57         const struct ctrl_ioregs *ioregs;
  58
  59         get_ioregs(&ioregs);
  60         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  61         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  62         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  63         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  64         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  65         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  66         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  67         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  68         writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  69 }
  70
  71 /* DDR3 specific IO settings */
  72 static void io_settings_ddr3(void)
  73 {
  74         u32 io_settings = 0;
  75         const struct ctrl_ioregs *ioregs;
  76
  77         get_ioregs(&ioregs);
  78         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
  79         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  80         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  81
  82         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
  83         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  84         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  85
  86         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  87         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  88
  89         if (!is_dra7xx()) {
  90                 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  91                 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  92         }
  93
  94         /* omap5432 does not use lpddr2 */
  95         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  96
  97         writel(ioregs->ctrl_emif_sdram_config_ext,
  98                (*ctrl)->control_emif1_sdram_config_ext);
  99         if (!is_dra72x())
 100                 writel(ioregs->ctrl_emif_sdram_config_ext,
 101                        (*ctrl)->control_emif2_sdram_config_ext);
 102
 103         if (is_omap54xx()) {
 104                 /* Disable DLL select */
 105                 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
 106                                                         & 0xFFEFFFFF);
 107                 writel(io_settings,
 108                         (*ctrl)->control_port_emif1_sdram_config);
 109
 110                 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
 111                                                         & 0xFFEFFFFF);
 112                 writel(io_settings,
 113                         (*ctrl)->control_port_emif2_sdram_config);
 114         } else {
 115                 writel(ioregs->ctrl_ddr_ctrl_ext_0,
 116                                 (*ctrl)->control_ddr_control_ext_0);
 117         }
 118 }
 119
 120 /*
 121  * Some tuning of IOs for optimal power and performance
 122  */
 123 void do_io_settings(void)
 124 {
 125         u32 io_settings = 0, mask = 0;
 126         struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
 127
 128         /* Impedance settings EMMC, C2C 1,2, hsi2 */
 129         mask = (ds_mask << 2) | (ds_mask << 8) |
 130                 (ds_mask << 16) | (ds_mask << 18);
 131         io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
 132                                 (~mask);
 133         io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
 134                         (ds_45_ohm << 18) | (ds_60_ohm << 2);
 135         writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
 136
 137         /* Impedance settings Mcspi2 */
 138         mask = (ds_mask << 30);
 139         io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
 140                         (~mask);
 141         io_settings |= (ds_60_ohm << 30);
 142         writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
 143
 144         /* Impedance settings C2C 3,4 */
 145         mask = (ds_mask << 14) | (ds_mask << 16);
 146         io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
 147                         (~mask);
 148         io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
 149         writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
 150
 151         /* Slew rate settings EMMC, C2C 1,2 */
 152         mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
 153         io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
 154                         (~mask);
 155         io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
 156         writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
 157
 158         /* Slew rate settings hsi2, Mcspi2 */
 159         mask = (sc_mask << 24) | (sc_mask << 28);
 160         io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
 161                         (~mask);
 162         io_settings |= (sc_fast << 28) | (sc_fast << 24);
 163         writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
 164
 165         /* Slew rate settings C2C 3,4 */
 166         mask = (sc_mask << 16) | (sc_mask << 18);
 167         io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
 168                         (~mask);
 169         io_settings |= (sc_na << 16) | (sc_na << 18);
 170         writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
 171
 172         /* impedance and slew rate settings for usb */
 173         mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
 174                 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
 175         io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
 176                         (~mask);
 177         io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
 178                        (ds_60_ohm << 23) | (sc_fast << 20) |
 179                        (sc_fast << 17) | (sc_fast << 14);
 180         writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
 181
 182         if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
 183                 io_settings_lpddr2();
 184         else
 185                 io_settings_ddr3();
 186 }
 187
 188 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
 189         {0x45, 0x1},    /* 12 MHz   */
 190         {-1, -1},       /* 13 MHz   */
 191         {0x63, 0x2},    /* 16.8 MHz */
 192         {0x57, 0x2},    /* 19.2 MHz */
 193         {0x20, 0x1},    /* 26 MHz   */
 194         {-1, -1},       /* 27 MHz   */
 195         {0x41, 0x3}     /* 38.4 MHz */
 196 };
 197
 198 void srcomp_enable(void)
 199 {
 200         u32 srcomp_value, mul_factor, div_factor, clk_val, i;
 201         u32 sysclk_ind  = get_sys_clk_index();
 202         u32 omap_rev    = omap_revision();
 203
 204         if (!is_omap54xx())
 205                 return;
 206
 207         mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
 208         div_factor = srcomp_parameters[sysclk_ind].divide_factor;
 209
 210         for (i = 0; i < 4; i++) {
 211                 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
 212                 srcomp_value &=
 213                         ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
 214                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 215                         (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 216                 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
 217         }
 218
 219         if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
 220                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 221                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 222                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 223
 224                 for (i = 0; i < 4; i++) {
 225                         srcomp_value =
 226                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 227                         srcomp_value &= ~PWRDWN_XS_MASK;
 228                         writel(srcomp_value,
 229                                (*ctrl)->control_srcomp_north_side + i*4);
 230
 231                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 232                                 & SRCODE_READ_XS_MASK) >>
 233                                 SRCODE_READ_XS_SHIFT) == 0)
 234                                 ;
 235
 236                         srcomp_value =
 237                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 238                         srcomp_value &= ~OVERRIDE_XS_MASK;
 239                         writel(srcomp_value,
 240                                (*ctrl)->control_srcomp_north_side + i*4);
 241                 }
 242         } else {
 243                 srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
 244                 srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
 245                                   DIVIDE_FACTOR_XS_MASK);
 246                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 247                                 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 248                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 249
 250                 for (i = 0; i < 4; i++) {
 251                         srcomp_value =
 252                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 253                         srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 254                         writel(srcomp_value,
 255                                (*ctrl)->control_srcomp_north_side + i*4);
 256
 257                         srcomp_value =
 258                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 259                         srcomp_value &= ~OVERRIDE_XS_MASK;
 260                         writel(srcomp_value,
 261                                (*ctrl)->control_srcomp_north_side + i*4);
 262                 }
 263
 264                 srcomp_value =
 265                         readl((*ctrl)->control_srcomp_east_side_wkup);
 266                 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 267                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 268
 269                 srcomp_value =
 270                         readl((*ctrl)->control_srcomp_east_side_wkup);
 271                 srcomp_value &= ~OVERRIDE_XS_MASK;
 272                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 273
 274                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 275                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 276                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 277
 278                 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 279                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 280                 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 281
 282                 for (i = 0; i < 4; i++) {
 283                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 284                                 & SRCODE_READ_XS_MASK) >>
 285                                 SRCODE_READ_XS_SHIFT) == 0)
 286                                 ;
 287
 288                         srcomp_value =
 289                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 290                         srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 291                         writel(srcomp_value,
 292                                (*ctrl)->control_srcomp_north_side + i*4);
 293                 }
 294
 295                 while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
 296                         SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
 297                         ;
 298
 299                 srcomp_value =
 300                         readl((*ctrl)->control_srcomp_east_side_wkup);
 301                 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 302                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 303         }
 304 }
 305 #endif
 306
 307 void config_data_eye_leveling_samples(u32 emif_base)
 308 {
 309         const struct ctrl_ioregs *ioregs;
 310
 311         get_ioregs(&ioregs);
 312
 313         /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 314         if (emif_base == EMIF1_BASE)
 315                 writel(ioregs->ctrl_emif_sdram_config_ext_final,
 316                        (*ctrl)->control_emif1_sdram_config_ext);
 317         else if (emif_base == EMIF2_BASE)
 318                 writel(ioregs->ctrl_emif_sdram_config_ext_final,
 319                        (*ctrl)->control_emif2_sdram_config_ext);
 320 }
 321
 322 void init_cpu_configuration(void)
 323 {
 324         u32 l2actlr;
 325
 326         asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
 327         /*
 328          * L2ACTLR: Ensure to enable the following:
 329          * 3: Disable clean/evict push to external
 330          * 4: Disable WriteUnique and WriteLineUnique transactions from master
 331          * 8: Disable DVM/CMO message broadcast
 332          */
 333         l2actlr |= 0x118;
 334         omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
 335 }
 336
 337 void init_omap_revision(void)
 338 {
 339         /*
 340          * For some of the ES2/ES1 boards ID_CODE is not reliable:
 341          * Also, ES1 and ES2 have different ARM revisions
 342          * So use ARM revision for identification
 343          */
 344         unsigned int rev = cortex_rev();
 345
 346         switch (readl(CONTROL_ID_CODE)) {
 347         case OMAP5430_CONTROL_ID_CODE_ES1_0:
 348                 *omap_si_rev = OMAP5430_ES1_0;
 349                 if (rev == MIDR_CORTEX_A15_R2P2)
 350                         *omap_si_rev = OMAP5430_ES2_0;
 351                 break;
 352         case OMAP5432_CONTROL_ID_CODE_ES1_0:
 353                 *omap_si_rev = OMAP5432_ES1_0;
 354                 if (rev == MIDR_CORTEX_A15_R2P2)
 355                         *omap_si_rev = OMAP5432_ES2_0;
 356                 break;
 357         case OMAP5430_CONTROL_ID_CODE_ES2_0:
 358                 *omap_si_rev = OMAP5430_ES2_0;
 359                 break;
 360         case OMAP5432_CONTROL_ID_CODE_ES2_0:
 361                 *omap_si_rev = OMAP5432_ES2_0;
 362                 break;
 363         case DRA762_CONTROL_ID_CODE_ES1_0:
 364                 *omap_si_rev = DRA762_ES1_0;
 365                 break;
 366         case DRA752_CONTROL_ID_CODE_ES1_0:
 367                 *omap_si_rev = DRA752_ES1_0;
 368                 break;
 369         case DRA752_CONTROL_ID_CODE_ES1_1:
 370                 *omap_si_rev = DRA752_ES1_1;
 371                 break;
 372         case DRA752_CONTROL_ID_CODE_ES2_0:
 373                 *omap_si_rev = DRA752_ES2_0;
 374                 break;
 375         case DRA722_CONTROL_ID_CODE_ES1_0:
 376                 *omap_si_rev = DRA722_ES1_0;
 377                 break;
 378         case DRA722_CONTROL_ID_CODE_ES2_0:
 379                 *omap_si_rev = DRA722_ES2_0;
 380                 break;
 381         case DRA722_CONTROL_ID_CODE_ES2_1:
 382                 *omap_si_rev = DRA722_ES2_1;
 383                 break;
 384         default:
 385                 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 386         }
 387         init_cpu_configuration();
 388 }
 389
 390 void init_package_revision(void)
 391 {
 392         unsigned int die_id[4] = { 0 };
 393         u8 package;
 394
 395         omap_die_id(die_id);
 396         package = (die_id[2] >> 16) & 0x3;
 397
 398         if (is_dra76x()) {
 399                 switch (package) {
 400                 case DRA762_ABZ_PACKAGE:
 401                         *omap_si_rev = DRA762_ABZ_ES1_0;
 402                         break;
 403                 case DRA762_ACD_PACKAGE:
 404                 default:
 405                         *omap_si_rev = DRA762_ACD_ES1_0;
 406                         break;
 407                 }
 408         }
 409 }
 410
 411 void omap_die_id(unsigned int *die_id)
 412 {
 413         die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
 414         die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
 415         die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
 416         die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
 417 }
 418
 419 void reset_cpu(ulong ignored)
 420 {
 421         u32 omap_rev = omap_revision();
 422
 423         /*
 424          * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
 425          * So use cold reset in case instead.
 426          */
 427         if (omap_rev == OMAP5430_ES1_0)
 428                 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
 429         else
 430                 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
 431 }
 432
 433 u32 warm_reset(void)
 434 {
 435         return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 436 }
 437
 438 void setup_warmreset_time(void)
 439 {
 440         u32 rst_time, rst_val;
 441
 442         /*
 443          * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
 444          * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
 445          * into microsec and passing the value.
 446          */
 447         rst_time = usec_to_32k(CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC)
 448                 << RSTTIME1_SHIFT;
 449
 450         if (rst_time > RSTTIME1_MASK)
 451                 rst_time = RSTTIME1_MASK;
 452
 453         rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
 454         rst_val |= rst_time;
 455         writel(rst_val, (*prcm)->prm_rsttime);
 456 }
 457
 458 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 459                                  u32 cpu_rev_comb, u32 cpu_variant,
 460                                  u32 cpu_rev)
 461 {
 462         omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
 463 }
 464
 465 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
 466                           u32 cpu_variant, u32 cpu_rev)
 467 {
 468
 469 #ifdef CONFIG_ARM_ERRATA_801819
 470         /*
 471          * DRA72x processors are uniprocessors and DONOT have
 472          * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
 473          * Extensions) Hence the erratum workaround is not applicable for
 474          * DRA72x processors.
 475          */
 476         if (is_dra72x())
 477                 acr &= ~((0x3 << 23) | (0x3 << 25));
 478 #endif
 479         omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
 480 }
 481
 482 #if defined(CONFIG_PALMAS_POWER)
 483 __weak void board_mmc_poweron_ldo(uint voltage)
 484 {
 485         palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
 486 }
 487
 488 void vmmc_pbias_config(uint voltage)
 489 {
 490         u32 value = 0;
 491
 492         value = readl((*ctrl)->control_pbias);
 493         value &= ~SDCARD_PWRDNZ;
 494         writel(value, (*ctrl)->control_pbias);
 495         udelay(10); /* wait 10 us */
 496         value &= ~SDCARD_BIAS_PWRDNZ;
 497         writel(value, (*ctrl)->control_pbias);
 498
 499         board_mmc_poweron_ldo(voltage);
 500
 501         value = readl((*ctrl)->control_pbias);
 502         value |= SDCARD_BIAS_PWRDNZ;
 503         writel(value, (*ctrl)->control_pbias);
 504         udelay(150); /* wait 150 us */
 505         value |= SDCARD_PWRDNZ;
 506         writel(value, (*ctrl)->control_pbias);
 507         udelay(150); /* wait 150 us */
 508 }
 509 #endif