2 * Copyright 2016 Texas Instruments, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
12 #include <asm/omap_common.h>
13 #include <asm/arch-omap5/sys_proto.h>
15 #ifdef CONFIG_TI_SECURE_DEVICE
17 /* Give zero values if not already defined */
18 #ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
19 #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
21 #ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
22 #define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
25 static u32 hs_irq_skip[] = {
26 8, /* Secure violation reporting interrupt */
27 15, /* One interrupt for SDMA by secure world */
28 118 /* One interrupt for Crypto DMA by secure world */
31 static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
36 int len, i, old_cnt, new_cnt;
41 * Increase the size of the fdt
42 * so we have some breathing room
44 ret = fdt_increase_size(fdt, 512);
46 printf("Could not increase size of device tree: %s\n",
51 /* Reserve IRQs that are used/needed by secure world */
52 path = "/ocp/crossbar";
53 offs = fdt_path_offset(fdt, path);
55 debug("Node %s not found.\n", path);
59 /* Get current entries */
60 p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
62 old_cnt = len / sizeof(u32);
66 new_cnt = sizeof(hs_irq_skip) /
67 sizeof(hs_irq_skip[0]);
69 /* Create new/updated skip list for HS parts */
70 temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
71 for (i = 0; i < new_cnt; i++)
72 temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
73 for (i = 0; i < old_cnt; i++)
74 temp[i + new_cnt] = p_data[i];
76 /* Blow away old data and set new data */
77 fdt_delprop(fdt, offs, "ti,irqs-skip");
78 ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
80 (old_cnt + new_cnt) * sizeof(u32));
83 /* Check if the update worked */
85 printf("Could not add ti,irqs-skip property to node %s: %s\n",
86 path, fdt_strerror(ret));
93 static int ft_hs_disable_rng(void *fdt, bd_t *bd)
99 /* Make HW RNG reserved for secure world use */
101 offs = fdt_path_offset(fdt, path);
103 debug("Node %s not found.\n", path);
106 ret = fdt_setprop_string(fdt, offs,
107 "status", "disabled");
109 printf("Could not add status property to node %s: %s\n",
110 path, fdt_strerror(ret));
116 #if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
117 (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
118 static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
126 * Update SRAM reservations on secure devices. The OCMC RAM
127 * is always reserved for secure use from the start of that
130 path = "/ocp/ocmcram@40300000/sram-hs";
131 offs = fdt_path_offset(fdt, path);
133 debug("Node %s not found.\n", path);
137 /* relative start offset */
138 temp[0] = cpu_to_fdt32(0);
139 /* reservation size */
140 temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
141 CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
142 fdt_delprop(fdt, offs, "reg");
143 ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
145 printf("Could not add reg property to node %s: %s\n",
146 path, fdt_strerror(ret));
153 static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
156 #if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE != 0)
157 static int ft_hs_fixup_dram(void *fdt, bd_t *bd)
159 const char *path, *subpath;
161 u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
162 u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
166 /* If start address is zero, place at end of DRAM */
167 if (0 == sec_mem_start)
169 (CONFIG_SYS_SDRAM_BASE +
170 (omap_sdram_size() - sec_mem_size));
172 /* Delete any original secure_reserved node */
173 path = "/reserved-memory/secure_reserved";
174 offs = fdt_path_offset(fdt, path);
176 fdt_del_node(fdt, offs);
178 /* Add new secure_reserved node */
179 path = "/reserved-memory";
180 offs = fdt_path_offset(fdt, path);
182 debug("Node %s not found\n", path);
184 subpath = "reserved-memory";
185 offs = fdt_path_offset(fdt, path);
186 offs = fdt_add_subnode(fdt, offs, subpath);
188 printf("Could not create %s%s node.\n", path, subpath);
191 path = "/reserved-memory";
192 offs = fdt_path_offset(fdt, path);
193 two = cpu_to_fdt32(2);
194 fdt_setprop(fdt, offs, "#address-cells", &two, sizeof(two));
195 fdt_setprop(fdt, offs, "#size-cells", &two, sizeof(two));
196 fdt_setprop(fdt, offs, "ranges", NULL, 0);
199 subpath = "secure_reserved";
200 offs = fdt_add_subnode(fdt, offs, subpath);
202 printf("Could not create %s%s node.\n", path, subpath);
206 temp[0] = cpu_to_fdt64(((u64)sec_mem_start));
207 temp[1] = cpu_to_fdt64(((u64)sec_mem_size));
208 fdt_setprop_string(fdt, offs, "compatible",
209 "ti,dra7-secure-memory");
210 fdt_setprop_string(fdt, offs, "status", "okay");
211 fdt_setprop(fdt, offs, "no-map", NULL, 0);
212 fdt_setprop(fdt, offs, "reg", temp, sizeof(temp));
217 static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; }
220 static int ft_hs_add_tee(void *fdt, bd_t *bd)
222 const char *path, *subpath;
225 extern int tee_loaded;
230 offs = fdt_path_offset(fdt, path);
232 subpath = "firmware";
233 offs = fdt_add_subnode(fdt, offs, subpath);
235 printf("Could not create %s node.\n", subpath);
240 offs = fdt_add_subnode(fdt, offs, subpath);
242 printf("Could not create %s node.\n", subpath);
246 fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
247 fdt_setprop_string(fdt, offs, "method", "smc");
252 static void ft_hs_fixups(void *fdt, bd_t *bd)
254 /* Check we are running on an HS/EMU device type */
255 if (GP_DEVICE != get_device_type()) {
256 if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
257 (ft_hs_disable_rng(fdt, bd) == 0) &&
258 (ft_hs_fixup_sram(fdt, bd) == 0) &&
259 (ft_hs_fixup_dram(fdt, bd) == 0) &&
260 (ft_hs_add_tee(fdt, bd) == 0))
263 printf("ERROR: Incorrect device type (GP) detected!");
265 /* Fixup failed or wrong device type */
269 static void ft_hs_fixups(void *fdt, bd_t *bd)
272 #endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
274 #if defined(CONFIG_TARGET_DRA7XX_EVM) || defined(CONFIG_TARGET_AM57XX_EVM)
275 #define OPP_DSP_CLK_NUM 3
276 #define OPP_IVA_CLK_NUM 2
277 #define OPP_GPU_CLK_NUM 2
279 const char *dra7_opp_dsp_clk_names[OPP_DSP_CLK_NUM] = {
285 const char *dra7_opp_iva_clk_names[OPP_IVA_CLK_NUM] = {
290 const char *dra7_opp_gpu_clk_names[OPP_GPU_CLK_NUM] = {
295 /* DSPEVE voltage domain */
296 u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
298 {600000000, 600000000, 400000000}, /* OPP_NOM */
299 {700000000, 700000000, 466666667}, /* OPP_OD */
300 {750000000, 750000000, 500000000}, /* OPP_HIGH */
303 /* IVA voltage domain */
304 u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
306 {1165000000, 388333334}, /* OPP_NOM */
307 {860000000, 430000000}, /* OPP_OD */
308 {1064000000, 532000000}, /* OPP_HIGH */
311 /* GPU voltage domain */
312 u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = {
314 {1277000000, 425666667}, /* OPP_NOM */
315 {1000000000, 500000000}, /* OPP_OD */
316 {1064000000, 532000000}, /* OPP_HIGH */
319 static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
321 int offs, node_offs, ret, i;
324 offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
326 debug("Could not find cm_core_aon clocks node path offset : %s\n",
331 for (i = 0; i < num; i++) {
332 node_offs = fdt_subnode_offset(fdt, offs, names[i]);
334 debug("Could not find clock sub-node %s: %s\n",
335 names[i], fdt_strerror(node_offs));
339 phandle = fdt_get_phandle(fdt, node_offs);
341 debug("Could not find phandle for clock %s\n",
346 ret = fdt_setprop_u32(fdt, node_offs, "assigned-clocks",
349 debug("Could not add assigned-clocks property to clock node %s: %s\n",
350 names[i], fdt_strerror(ret));
354 ret = fdt_setprop_u32(fdt, node_offs, "assigned-clock-rates",
357 debug("Could not add assigned-clock-rates property to clock node %s: %s\n",
358 names[i], fdt_strerror(ret));
366 static void ft_opp_clock_fixups(void *fdt, bd_t *bd)
368 const char **clk_names;
372 if (!is_dra72x() && !is_dra7xx())
375 /* fixup DSP clocks */
376 clk_names = dra7_opp_dsp_clk_names;
377 clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
378 ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
380 printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
385 /* fixup IVA clocks */
386 clk_names = dra7_opp_iva_clk_names;
387 clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)];
388 ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM);
390 printf("ft_fixup_clocks failed for IVA voltage domain: %s\n",
395 /* fixup GPU clocks */
396 clk_names = dra7_opp_gpu_clk_names;
397 clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)];
398 ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM);
400 printf("ft_fixup_clocks failed for GPU voltage domain: %s\n",
406 static void ft_opp_clock_fixups(void *fdt, bd_t *bd) { }
407 #endif /* CONFIG_TARGET_DRA7XX_EVM || CONFIG_TARGET_AM57XX_EVM */
410 * Place for general cpu/SoC FDT fixups. Board specific
411 * fixups should remain in the board files which is where
412 * this function should be called from.
414 void ft_cpu_setup(void *fdt, bd_t *bd)
416 ft_hs_fixups(fdt, bd);
417 ft_opp_clock_fixups(fdt, bd);