arch/arm/mach-omap2/am33xx/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * DDR Configuration for AM33xx devices.
   4  *
   5  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <common.h>
   9 #include <log.h>
  10 #include <asm/arch/cpu.h>
  11 #include <asm/arch/ddr_defs.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/io.h>
  14 #include <asm/emif.h>
  15
  16 /**
  17  * Base address for EMIF instances
  18  */
  19 static struct emif_reg_struct *emif_reg[2] = {
  20                                 (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
  21                                 (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
  22
  23 /**
  24  * Base addresses for DDR PHY cmd/data regs
  25  */
  26 static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
  27                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
  28                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
  29
  30 static struct ddr_data_regs *ddr_data_reg[2] = {
  31                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
  32                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
  33
  34 /**
  35  * Base address for ddr io control instances
  36  */
  37 static struct ddr_cmdtctrl *ioctrl_reg = {
  38                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  39
  40 static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
  41 {
  42         u32 mr;
  43
  44         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  45         writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  46
  47         mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
  48         debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
  49         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  50             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  51             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  52                 return mr & 0xff;
  53         else
  54                 return mr;
  55 }
  56
  57 static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
  58 {
  59         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  60         writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  61         writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
  62 }
  63
  64 static void configure_mr(int nr, u32 cs)
  65 {
  66         u32 mr_addr;
  67
  68         while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  69                 ;
  70         set_mr(nr, cs, LPDDR2_MR10, 0x56);
  71
  72         set_mr(nr, cs, LPDDR2_MR1, 0x43);
  73         set_mr(nr, cs, LPDDR2_MR2, 0x2);
  74
  75         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  76         set_mr(nr, cs, mr_addr, 0x2);
  77 }
  78
  79 /*
  80  * Configure EMIF4D5 registers and MR registers For details about these magic
  81  * values please see the EMIF registers section of the TRM.
  82  */
  83 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  84 {
  85 #ifdef CONFIG_AM43XX
  86         struct prm_device_inst *prm_device =
  87                         (struct prm_device_inst *)PRM_DEVICE_INST;
  88 #endif
  89
  90         writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
  91         writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
  92         writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  93
  94         writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
  95         writel(regs->emif_rd_wr_lvl_rmp_win,
  96                &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
  97         writel(regs->emif_rd_wr_lvl_rmp_ctl,
  98                &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
  99         writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 100         writel(regs->emif_rd_wr_exec_thresh,
 101                &emif_reg[nr]->emif_rd_wr_exec_thresh);
 102
 103         /*
 104          * for most SOCs these registers won't need to be changed so only
 105          * write to these registers if someone explicitly has set the
 106          * register's value.
 107          */
 108         if(regs->emif_cos_config) {
 109                 writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
 110                 writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
 111                 writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
 112                 writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
 113         }
 114
 115         /*
 116          * Sequence to ensure that the PHY is in a known state prior to
 117          * startting hardware leveling.  Also acts as to latch some state from
 118          * the EMIF into the PHY.
 119          */
 120         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 121         writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
 122         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 123
 124         clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
 125                         EMIF_REG_INITREF_DIS_MASK);
 126
 127         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 128         writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 129
 130         /* Wait 1ms because of L3 timeout error */
 131         udelay(1000);
 132
 133         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 134         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 135
 136 #ifdef CONFIG_AM43XX
 137         /*
 138          * Disable EMIF_DEVOFF
 139          * -> Cold Boot: This is just rewriting the default register value.
 140          * -> RTC Resume: Must disable DEVOFF before leveling.
 141          */
 142         writel(0, &prm_device->emif_ctrl);
 143 #endif
 144
 145         /* Perform hardware leveling for DDR3 */
 146         if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
 147                 writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
 148                        0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 149                 writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
 150                        0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 151
 152                 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
 153
 154                 /* Enable read leveling */
 155                 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 156
 157                 /* Wait 1ms because of L3 timeout error */
 158                 udelay(1000);
 159
 160                 /*
 161                  * Enable full read and write leveling.  Wait for read and write
 162                  * leveling bit to clear RDWRLVLFULL_START bit 31
 163                  */
 164                 while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
 165                       != 0)
 166                         ;
 167
 168                 /* Check the timeout register to see if leveling is complete */
 169                 if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
 170                         puts("DDR3 H/W leveling incomplete with errors\n");
 171
 172         } else {
 173                 /* DDR2 */
 174                 configure_mr(nr, 0);
 175                 configure_mr(nr, 1);
 176         }
 177 }
 178
 179 /**
 180  * Configure SDRAM
 181  */
 182 void config_sdram(const struct emif_regs *regs, int nr)
 183 {
 184 #ifdef CONFIG_TI816X
 185         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 186         writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
 187         writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 188         writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* initially a large refresh period */
 189         writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* trigger initialization           */
 190         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 191 #else
 192         if (regs->zq_config) {
 193                 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 194                 writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 195                 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 196
 197                 /* Trigger initialization */
 198                 writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
 199                 /* Wait 1ms because of L3 timeout error */
 200                 udelay(1000);
 201
 202                 /* Write proper sdram_ref_cref_ctrl value */
 203                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 204                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 205         }
 206         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 207         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 208         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 209
 210         /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
 211         if (regs->ocp_config)
 212                 writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
 213 #endif
 214 }
 215
 216 /**
 217  * Set SDRAM timings
 218  */
 219 void set_sdram_timings(const struct emif_regs *regs, int nr)
 220 {
 221         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
 222         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
 223         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
 224         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
 225         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
 226         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 227 }
 228
 229 /*
 230  * Configure EXT PHY registers for software leveling
 231  */
 232 static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
 233 {
 234         u32 *ext_phy_ctrl_base = 0;
 235         u32 *emif_ext_phy_ctrl_base = 0;
 236         __maybe_unused const u32 *ext_phy_ctrl_const_regs;
 237         u32 i = 0;
 238         __maybe_unused u32 size;
 239
 240         ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
 241         emif_ext_phy_ctrl_base =
 242                         (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 243
 244         /* Configure external phy control timing registers */
 245         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 246                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 247                 /* Update shadow registers */
 248                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 249         }
 250
 251 #ifdef CONFIG_AM43XX
 252         /*
 253          * External phy 6-24 registers do not change with ddr frequency.
 254          * These only need to be set on DDR2 on AM43xx.
 255          */
 256         emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
 257
 258         if (!size)
 259                 return;
 260
 261         for (i = 0; i < size; i++) {
 262                 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
 263                 /* Update shadow registers */
 264                 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
 265         }
 266 #endif
 267 }
 268
 269 /*
 270  * Configure EXT PHY registers for hardware leveling
 271  */
 272 static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
 273 {
 274         /*
 275          * Enable hardware leveling on the EMIF.  For details about these
 276          * magic values please see the EMIF registers section of the TRM.
 277          */
 278         if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
 279                 /* PHY_INVERT_CLKOUT = 1 */
 280                 writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 281                 writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
 282         } else {
 283                 /* PHY_INVERT_CLKOUT = 0 */
 284                 writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 285                 writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
 286         }
 287
 288         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
 289         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
 290         writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
 291         writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
 292         writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
 293         writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
 294         writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
 295         writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
 296         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
 297         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
 298         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
 299         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
 300         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
 301         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
 302         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
 303         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
 304         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
 305         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
 306         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
 307         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
 308         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
 309         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
 310         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
 311         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
 312         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
 313         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
 314         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
 315         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
 316         writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 317         writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 318
 319         /*
 320          * Sequence to ensure that the PHY is again in a known state after
 321          * hardware leveling.
 322          */
 323         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 324         writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
 325         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 326 }
 327
 328 /**
 329  * Configure DDR PHY
 330  */
 331 void config_ddr_phy(const struct emif_regs *regs, int nr)
 332 {
 333         /*
 334          * Disable initialization and refreshes for now until we finish
 335          * programming EMIF regs and set time between rising edge of
 336          * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
 337          * We currently hardcode a value based on a max expected frequency
 338          * of 400MHz.
 339          */
 340         writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
 341                 &emif_reg[nr]->emif_sdram_ref_ctrl);
 342
 343         writel(regs->emif_ddr_phy_ctlr_1,
 344                 &emif_reg[nr]->emif_ddr_phy_ctrl_1);
 345         writel(regs->emif_ddr_phy_ctlr_1,
 346                 &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 347
 348         if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
 349                 if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
 350                         ext_phy_settings_hwlvl(regs, nr);
 351                 else
 352                         ext_phy_settings_swlvl(regs, nr);
 353         }
 354 }
 355
 356 /**
 357  * Configure DDR CMD control registers
 358  */
 359 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 360 {
 361         if (!cmd)
 362                 return;
 363
 364         writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
 365         writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 366
 367         writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
 368         writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 369
 370         writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
 371         writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 372 }
 373
 374 /**
 375  * Configure DDR DATA registers
 376  */
 377 void config_ddr_data(const struct ddr_data *data, int nr)
 378 {
 379         int i;
 380
 381         if (!data)
 382                 return;
 383
 384         for (i = 0; i < DDR_DATA_REGS_NR; i++) {
 385                 writel(data->datardsratio0,
 386                         &(ddr_data_reg[nr]+i)->dt0rdsratio0);
 387                 writel(data->datawdsratio0,
 388                         &(ddr_data_reg[nr]+i)->dt0wdsratio0);
 389                 writel(data->datawiratio0,
 390                         &(ddr_data_reg[nr]+i)->dt0wiratio0);
 391                 writel(data->datagiratio0,
 392                         &(ddr_data_reg[nr]+i)->dt0giratio0);
 393                 writel(data->datafwsratio0,
 394                         &(ddr_data_reg[nr]+i)->dt0fwsratio0);
 395                 writel(data->datawrsratio0,
 396                         &(ddr_data_reg[nr]+i)->dt0wrsratio0);
 397         }
 398 }
 399
 400 void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 401 {
 402         if (!ioregs)
 403                 return;
 404
 405         writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
 406         writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
 407         writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
 408         writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
 409         writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
 410 #ifdef CONFIG_AM43XX
 411         writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
 412         writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
 413         writel(ioregs->emif_sdram_config_ext,
 414                &ioctrl_reg->emif_sdram_config_ext);
 415 #endif
 416 }