arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Marvell International Ltd. and its affiliates
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <spl.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/cpu.h>
  11 #include <asm/arch/soc.h>
  12
  13 #include "high_speed_env_spec.h"
  14 #include "board_env_spec.h"
  15
  16 #define SERDES_VERSION  "2.1.5"
  17 #define ENDED_OK        "High speed PHY - Ended Successfully\n"
  18
  19 static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
  20
  21 extern MV_BIN_SERDES_CFG *serdes_info_tbl[];
  22
  23 extern u8 rd78460gp_twsi_dev[];
  24 extern u8 db88f78xx0rev2_twsi_dev[];
  25
  26 u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs);
  27 int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
  28 int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
  29
  30 #define MV_BOARD_PEX_MODULE_ADDR                0x23
  31 #define MV_BOARD_PEX_MODULE_ID                  1
  32 #define MV_BOARD_ETM_MODULE_ID                  2
  33
  34 #define PEX_MODULE_DETECT               1
  35 #define ETM_MODULE_DETECT               2
  36
  37 #define PEX_MODE_GET(satr)              ((satr & 0x6) >> 1)
  38 #define PEX_CAPABILITY_GET(satr, port)  ((satr >> port) & 1)
  39 #define MV_PEX_UNIT_TO_IF(pex_unit)     ((pex_unit < 3) ? (pex_unit * 4) : 9)
  40
  41 /* Static parametes */
  42 static int config_module;
  43 static int switch_module;
  44
  45 /* Local function */
  46 static u32 board_id_get(void)
  47 {
  48 #if defined(CONFIG_DB_88F78X60)
  49         return DB_88F78XX0_BP_ID;
  50 #elif defined(CONFIG_RD_88F78460_SERVER)
  51         return RD_78460_SERVER_ID;
  52 #elif defined(CONFIG_RD_78460_SERVER_REV2)
  53         return RD_78460_SERVER_REV2_ID;
  54 #elif defined(CONFIG_DB_78X60_PCAC)
  55         return DB_78X60_PCAC_ID;
  56 #elif defined(CONFIG_DB_88F78X60_REV2)
  57         return DB_88F78XX0_BP_REV2_ID;
  58 #elif defined(CONFIG_RD_78460_NAS)
  59         return RD_78460_NAS_ID;
  60 #elif defined(CONFIG_DB_78X60_AMC)
  61         return DB_78X60_AMC_ID;
  62 #elif defined(CONFIG_DB_78X60_PCAC_REV2)
  63         return DB_78X60_PCAC_REV2_ID;
  64 #elif defined(CONFIG_DB_784MP_GP)
  65         return DB_784MP_GP_ID;
  66 #elif defined(CONFIG_RD_78460_CUSTOMER)
  67         return RD_78460_CUSTOMER_ID;
  68 #else
  69         /*
  70          * Return 0 here for custom board as this should not be used
  71          * for custom boards.
  72          */
  73         return 0;
  74 #endif
  75 }
  76
  77 __weak u8 board_sat_r_get(u8 dev_num, u8 reg)
  78 {
  79         u8 data;
  80         u8 *dev;
  81         u32 board_id = board_id_get();
  82         int ret;
  83
  84         switch (board_id) {
  85         case DB_78X60_AMC_ID:
  86         case DB_78X60_PCAC_REV2_ID:
  87         case RD_78460_CUSTOMER_ID:
  88         case RD_78460_SERVER_ID:
  89         case RD_78460_SERVER_REV2_ID:
  90         case DB_78X60_PCAC_ID:
  91                 return (0x1 << 1) | 1;
  92         case FPGA_88F78XX0_ID:
  93         case RD_78460_NAS_ID:
  94                 return (0x0 << 1) | 1;
  95         case DB_784MP_GP_ID:
  96                 dev = rd78460gp_twsi_dev;
  97
  98                 break;
  99         case DB_88F78XX0_BP_ID:
 100         case DB_88F78XX0_BP_REV2_ID:
 101                 dev = db88f78xx0rev2_twsi_dev;
 102                 break;
 103
 104         default:
 105                 return 0;
 106         }
 107
 108         /* Read MPP module ID */
 109         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 110         ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
 111         if (ret)
 112                 return MV_ERROR;
 113
 114         return data;
 115 }
 116
 117 static int board_modules_scan(void)
 118 {
 119         u8 val;
 120         u32 board_id = board_id_get();
 121         int ret;
 122
 123         /* Perform scan only for DB board */
 124         if ((board_id == DB_88F78XX0_BP_ID) ||
 125             (board_id == DB_88F78XX0_BP_REV2_ID)) {
 126                 /* reset modules flags */
 127                 config_module = 0;
 128
 129                 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 130
 131                 /* SERDES module (only PEX model is supported now) */
 132                 ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1);
 133                 if (ret)
 134                         return MV_ERROR;
 135
 136                 if (val == MV_BOARD_PEX_MODULE_ID)
 137                         config_module = PEX_MODULE_DETECT;
 138                 if (val == MV_BOARD_ETM_MODULE_ID)
 139                         config_module = ETM_MODULE_DETECT;
 140         } else if (board_id == RD_78460_NAS_ID) {
 141                 switch_module = 0;
 142                 if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0)
 143                         switch_module = 1;
 144         }
 145
 146         return MV_OK;
 147 }
 148
 149 u32 pex_max_unit_get(void)
 150 {
 151         /*
 152          * TODO:
 153          * Right now only MV78460 is supported. Other SoC's might need
 154          * a different value here.
 155          */
 156         return MV_PEX_MAX_UNIT;
 157 }
 158
 159 u32 pex_max_if_get(void)
 160 {
 161         /*
 162          * TODO:
 163          * Right now only MV78460 is supported. Other SoC's might need
 164          * a different value here.
 165          */
 166         return MV_PEX_MAX_IF;
 167 }
 168
 169 u8 board_cpu_freq_get(void)
 170 {
 171         u32 sar;
 172         u32 sar_msb;
 173
 174         sar = reg_read(MPP_SAMPLE_AT_RESET(0));
 175         sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1));
 176         return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
 177 }
 178
 179 __weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
 180 {
 181         u32 board_id;
 182         u32 serdes_cfg_val = 0; /* default */
 183
 184         board_id = board_id_get();
 185
 186         switch (board_id) {
 187         case DB_784MP_GP_ID:
 188                 serdes_cfg_val = 0;
 189                 break;
 190         }
 191
 192         return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val];
 193 }
 194
 195 u16 ctrl_model_get(void)
 196 {
 197         /*
 198          * SoC version can't be autodetected. So we need to rely on a define
 199          * from the config system here.
 200          */
 201 #if defined(CONFIG_MV78230)
 202         return MV_78230_DEV_ID;
 203 #elif defined(CONFIG_MV78260)
 204         return MV_78260_DEV_ID;
 205 #else
 206         return MV_78460_DEV_ID;
 207 #endif
 208 }
 209
 210 u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
 211 {
 212         if (line_num < 8)
 213                 return (info->line0_7 >> (line_num << 2)) & 0xF;
 214         else
 215                 return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
 216 }
 217
 218 static int serdes_max_lines_get(void)
 219 {
 220         switch (ctrl_model_get()) {
 221         case MV_78230_DEV_ID:
 222                 return 7;
 223         case MV_78260_DEV_ID:
 224                 return 12;
 225         case MV_78460_DEV_ID:
 226                 return 16;
 227         }
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * Tests have shown that on some boards the default width of the
 234  * configuration pulse for the PEX link detection might lead to
 235  * non-established PCIe links (link down). Especially under certain
 236  * conditions (higher temperature) and with specific PCIe devices.
 237  * To enable a board-specific detection pulse width this weak
 238  * array "serdes_pex_pulse_width[4]" is introduced which can be
 239  * overwritten if needed by a board-specific version. If the board
 240  * code does not provide a non-weak version of this variable, the
 241  * default value will be used. So nothing is changed from the
 242  * current setup on the supported board.
 243  */
 244 __weak u8 serdes_pex_pulse_width[4] = { 2, 2, 2, 2 };
 245
 246 int serdes_phy_config(void)
 247 {
 248         int status = MV_OK;
 249         u32 line_cfg;
 250         u8 line_num;
 251         /* addr/value for each line @ every setup step */
 252         u32 addr[16][11], val[16][11];
 253         u8 pex_unit, pex_line_num;
 254         u8 sgmii_port = 0;
 255         u32 tmp;
 256         u32 in_direct;
 257         u8 max_serdes_lines;
 258         MV_BIN_SERDES_CFG *info;
 259         u8 satr11;
 260         u8 sata_port;
 261         u8 freq;
 262         u8 device_rev;
 263         u32 rx_high_imp_mode;
 264         u16 ctrl_mode;
 265         u32 pex_if;
 266         u32 pex_if_num;
 267
 268         /*
 269          * Get max. serdes lines count
 270          */
 271         max_serdes_lines = serdes_max_lines_get();
 272         if (max_serdes_lines == 0)
 273                 return MV_OK;
 274
 275         satr11 = board_sat_r_get(1, 1);
 276         if ((u8) MV_ERROR == (u8) satr11)
 277                 return MV_ERROR;
 278
 279         board_modules_scan();
 280         memset(addr, 0, sizeof(addr));
 281         memset(val, 0, sizeof(val));
 282
 283         /* Check if DRAM is already initialized  */
 284         if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
 285             (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
 286                 DEBUG_INIT_S("High speed PHY - Version: ");
 287                 DEBUG_INIT_S(SERDES_VERSION);
 288                 DEBUG_INIT_S(" - 2nd boot - Skip\n");
 289                 return MV_OK;
 290         }
 291         DEBUG_INIT_S("High speed PHY - Version: ");
 292         DEBUG_INIT_S(SERDES_VERSION);
 293         DEBUG_INIT_S(" (COM-PHY-V20)\n");
 294
 295         /*
 296          * AVS :  disable AVS for frequency less than 1333
 297          */
 298         freq = board_cpu_freq_get();
 299         device_rev = mv_ctrl_rev_get();
 300
 301         if (device_rev == 2) {  /*   for B0 only */
 302                 u32 cpu_avs;
 303                 u8 fabric_freq;
 304                 cpu_avs = reg_read(CPU_AVS_CONTROL2_REG);
 305                 DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
 306                 cpu_avs &= ~(1 << 9);
 307
 308                 if ((0x4 == freq) || (0xB == freq)) {
 309                         u32 tmp2;
 310
 311                         tmp2 = reg_read(CPU_AVS_CONTROL0_REG);
 312                         DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2);
 313                         /* cpu upper limit = 1.1V  cpu lower limit = 0.9125V  */
 314                         tmp2 |= 0x0FF;
 315                         reg_write(CPU_AVS_CONTROL0_REG, tmp2);
 316                         DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2);
 317                         cpu_avs |= (1 << 9);    /* cpu avs enable */
 318                         cpu_avs |= (1 << 18);   /* AvsAvddDetEn enable  */
 319                         fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) &
 320                                        SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET;
 321                         if ((0xB == freq) && (5 == fabric_freq)) {
 322                                 u32 core_avs;
 323
 324                                 core_avs = reg_read(CORE_AVS_CONTROL_0REG);
 325                                 DEBUG_RD_REG(CORE_AVS_CONTROL_0REG, core_avs);
 326
 327                                 /*
 328                                  * Set core lower limit = 0.9V &
 329                                  * core upper limit = 0.9125V
 330                                  */
 331                                 core_avs &= ~(0xff);
 332                                 core_avs |= 0x0E;
 333                                 reg_write(CORE_AVS_CONTROL_0REG, core_avs);
 334                                 DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs);
 335
 336                                 core_avs = reg_read(CORE_AVS_CONTROL_2REG);
 337                                 DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs);
 338                                 core_avs |= (1 << 9);   /*  core AVS enable  */
 339                                 reg_write(CORE_AVS_CONTROL_2REG, core_avs);
 340                                 DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs);
 341
 342                                 tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
 343                                 DEBUG_RD_REG(GENERAL_PURPOSE_RESERVED0_REG,
 344                                              tmp2);
 345                                 tmp2 |= 0x1;    /*  AvsCoreAvddDetEn enable   */
 346                                 reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2);
 347                                 DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG,
 348                                              tmp2);
 349                         }
 350                 }
 351                 reg_write(CPU_AVS_CONTROL2_REG, cpu_avs);
 352                 DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
 353         }
 354
 355         info = board_serdes_cfg_get();
 356
 357         if (info == NULL) {
 358                 DEBUG_INIT_S("Hight speed PHY Error #1\n");
 359                 return MV_ERROR;
 360         }
 361         DEBUG_INIT_FULL_S("info->line0_7= 0x");
 362         DEBUG_INIT_FULL_D(info->line0_7, 8);
 363         DEBUG_INIT_FULL_S("   info->line8_15= 0x");
 364         DEBUG_INIT_FULL_D(info->line8_15, 8);
 365         DEBUG_INIT_FULL_S("\n");
 366
 367         if (config_module & ETM_MODULE_DETECT) {        /* step 0.9 ETM */
 368                 DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n");
 369                 reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111);
 370                 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111);
 371                 info->pex_mode[1] = PEX_BUS_DISABLED;   /* pex unit 1 is configure for ETM */
 372                 mdelay(100);
 373                 reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d);       /* SETM0 - start calibration         */
 374                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d);    /* SETM0 - start calibration         */
 375                 reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d);       /* SETM1 - start calibration         */
 376                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d);    /* SETM1 - start calibration         */
 377                 reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801);       /* SETM0 - SATA mode & 25MHz ref clk */
 378                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801);    /* SETM0 - SATA mode & 25MHz ref clk */
 379                 reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801);       /* SETM1 - SATA mode & 25MHz ref clk */
 380                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801);    /* SETM1 - SATA mode & 25MHz ref clk */
 381                 reg_write(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF);       /* SETM0 - G3 full swing AMP         */
 382                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF);    /* SETM0 - G3 full swing AMP         */
 383                 reg_write(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF);       /* SETM1 - G3 full swing AMP         */
 384                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF);    /* SETM1 - G3 full swing AMP         */
 385                 reg_write(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800);       /* SETM0 - 40 data bit width         */
 386                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800);    /* SETM0 - 40 data bit width         */
 387                 reg_write(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800);       /* SETM1 - 40 data bit width         */
 388                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800);    /* SETM1 - 40 data bit width         */
 389                 reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400);       /* lane0(serdes4)                    */
 390                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400);    /* lane0(serdes4)                    */
 391                 reg_write(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400);       /* lane3(serdes7)                    */
 392                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400);    /* lane3(serdes7)                    */
 393         }
 394
 395         /* STEP -1 [PEX-Only] First phase of PEX-PIPE Configuration: */
 396         DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n");
 397         for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
 398                 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
 399                         continue;
 400
 401                 /* 1.   GLOB_CLK_CTRL Reset and Clock Control */
 402                 reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
 403                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
 404
 405                 /* 2.   GLOB_TEST_CTRL Test Mode Control */
 406                 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) {
 407                         reg_write(PEX_PHY_ACCESS_REG(pex_unit),
 408                                   (0xC2 << 16) | 0x200);
 409                         DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
 410                                      (0xC2 << 16) | 0x200);
 411                 }
 412
 413                 /* 3.   GLOB_CLK_SRC_LO Clock Source Low */
 414                 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
 415                         reg_write(PEX_PHY_ACCESS_REG(pex_unit),
 416                                   (0xC3 << 16) | 0x0F);
 417                         DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
 418                                      (0xC3 << 16) | 0x0F);
 419                 }
 420
 421                 reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC5 << 16) | 0x11F);
 422                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
 423                              (0xC5 << 16) | 0x11F);
 424         }
 425
 426         /*
 427          * 2 Configure the desire PIN_PHY_GEN and do power down to the PU_PLL,
 428          * PU_RX,PU_TX. (bits[12:5])
 429          */
 430         DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n");
 431         for (line_num = 0; line_num < max_serdes_lines; line_num++) {
 432                 line_cfg = get_line_cfg(line_num, info);
 433                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
 434                         continue;
 435                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
 436                         continue;
 437                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
 438                         switch (line_num) {
 439                         case 4:
 440                         case 6:
 441                                 sata_port = 0;
 442                                 break;
 443                         case 5:
 444                                 sata_port = 1;
 445                                 break;
 446                         default:
 447                                 DEBUG_INIT_C
 448                                     ("SATA port error for serdes line: ",
 449                                      line_num, 2);
 450                                 return MV_ERROR;
 451                         }
 452                         tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
 453                         DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
 454                         tmp &= ~((0x1ff << 5) | 0x7);
 455                         tmp |= ((info->bus_speed & (1 << line_num)) != 0) ?
 456                                 (0x11 << 5) : 0x0;
 457
 458                         reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
 459                         DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
 460                 }
 461
 462                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
 463                         /*
 464                          * 4) Configure the desire PIN_PHY_GEN and do power
 465                          * down to the PU_PLL,PU_RX,PU_TX. (bits[12:5])
 466                          */
 467                         tmp = reg_read(SGMII_SERDES_CFG_REG(0));
 468                         DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
 469                         tmp &= ~((0x1ff << 5) | 0x7);
 470                         tmp |= 0x660;
 471                         reg_write(SGMII_SERDES_CFG_REG(0), tmp);
 472                         DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
 473                         continue;
 474                 }
 475
 476                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
 477                         sgmii_port = 0;
 478                 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
 479                         sgmii_port = 1;
 480                 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
 481                         sgmii_port = 2;
 482                 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
 483                         sgmii_port = 3;
 484                 else
 485                         continue;
 486
 487                 tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
 488                 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
 489                 tmp &= ~((0x1ff << 5) | 0x7);
 490                 tmp |= (((info->bus_speed & (1 << line_num)) != 0) ?
 491                         (0x88 << 5) : (0x66 << 5));
 492                 reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
 493                 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
 494         }
 495
 496         /* Step 3 - QSGMII enable */
 497         DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n");
 498         for (line_num = 0; line_num < max_serdes_lines; line_num++) {
 499                 line_cfg = get_line_cfg(line_num, info);
 500                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
 501                         /* QSGMII Active bit set to true */
 502                         tmp = reg_read(QSGMII_CONTROL_1_REG);
 503                         DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp);
 504                         tmp |= (1 << 30);
 505 #ifdef ERRATA_GL_6572255
 506                         tmp |= (1 << 27);
 507 #endif
 508                         reg_write(QSGMII_CONTROL_1_REG, tmp);
 509                         DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp);
 510                 }
 511         }
 512
 513         /* Step 4 - configure SERDES MUXes */
 514         DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n");
 515         if (config_module & ETM_MODULE_DETECT) {
 516                 reg_write(SERDES_LINE_MUX_REG_0_7, 0x40041111);
 517                 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x40041111);
 518         } else {
 519                 reg_write(SERDES_LINE_MUX_REG_0_7, info->line0_7);
 520                 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, info->line0_7);
 521         }
 522         reg_write(SERDES_LINE_MUX_REG_8_15, info->line8_15);
 523         DEBUG_WR_REG(SERDES_LINE_MUX_REG_8_15, info->line8_15);
 524
 525         /* Step 5: Activate the RX High Impedance Mode  */
 526         DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n");
 527         rx_high_imp_mode = 0x8080;
 528         if (device_rev == 2)    /*   for B0 only */
 529                 rx_high_imp_mode |= 4;
 530
 531         for (line_num = 0; line_num < max_serdes_lines; line_num++) {
 532                 /* for each serdes lane */
 533                 DEBUG_INIT_FULL_S("SERDES  ");
 534                 DEBUG_INIT_FULL_D_10(line_num, 2);
 535                 line_cfg = get_line_cfg(line_num, info);
 536                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) {
 537                         DEBUG_INIT_FULL_S(" unconnected ***\n");
 538                         continue;
 539                 }
 540                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
 541                         pex_unit = line_num >> 2;
 542                         pex_line_num = line_num % 4;
 543                         DEBUG_INIT_FULL_S(" - PEX unit ");
 544                         DEBUG_INIT_FULL_D_10(pex_unit, 1);
 545                         DEBUG_INIT_FULL_S(" line=  ");
 546                         DEBUG_INIT_FULL_D_10(pex_line_num, 1);
 547                         DEBUG_INIT_FULL_S("\n");
 548
 549                         /* Needed for PEX_PHY_ACCESS_REG macro */
 550                         if ((line_num > 7) &&
 551                             (info->pex_mode[3] == PEX_BUS_MODE_X8))
 552                                 /* lines 8 - 15 are belong to PEX3 in x8 mode */
 553                                 pex_unit = 3;
 554
 555                         if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
 556                                 continue;
 557
 558                         /*
 559                          * 8)  Activate the RX High Impedance Mode field
 560                          * (bit [2]) in register /PCIe_USB Control (Each MAC
 561                          * contain different Access to reach its
 562                          * Serdes-Regfile).
 563                          * [PEX-Only] Set bit[12]: The analog part latches idle
 564                          * if PU_TX = 1 and PU_PLL =1.
 565                          */
 566
 567                         /* Termination enable */
 568                         if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
 569                                 in_direct = (0x48 << 16) | (pex_line_num << 24) |
 570                                         0x1000 | rx_high_imp_mode;      /* x1 */
 571                         } else if ((info->pex_mode[pex_unit] ==
 572                                     PEX_BUS_MODE_X4) && (pex_line_num == 0))
 573                                 in_direct = (0x48 << 16) | (pex_line_num << 24) |
 574                                         0x1000 | (rx_high_imp_mode & 0xff);     /* x4 */
 575                         else
 576                                 in_direct = 0;
 577
 578                         if (in_direct) {
 579                                 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
 580                                           in_direct);
 581                                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
 582                                              in_direct);
 583                         }
 584
 585                         continue;
 586                 }
 587
 588                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
 589                         /*
 590                          * port 0 for serdes lines 4,6,  and port 1 for
 591                          * serdes lines 5
 592                          */
 593                         sata_port = line_num & 1;
 594                         DEBUG_INIT_FULL_S(" - SATA port  ");
 595                         DEBUG_INIT_FULL_D_10(sata_port, 2);
 596                         DEBUG_INIT_FULL_S("\n");
 597                         reg_write(SATA_COMPHY_CTRL_REG(sata_port),
 598                                   rx_high_imp_mode);
 599                         DEBUG_WR_REG(SATA_COMPHY_CTRL_REG(sata_port),
 600                                      rx_high_imp_mode);
 601                         continue;
 602                 }
 603
 604                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
 605                         DEBUG_INIT_FULL_S(" - QSGMII\n");
 606                         reg_write(SGMII_COMPHY_CTRL_REG(0), rx_high_imp_mode);
 607                         DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(0),
 608                                      rx_high_imp_mode);
 609                         continue;
 610                 }
 611
 612                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
 613                         sgmii_port = 0;
 614                 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
 615                         sgmii_port = 1;
 616                 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
 617                         sgmii_port = 2;
 618                 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
 619                         sgmii_port = 3;
 620                 else
 621                         continue;
 622                 DEBUG_INIT_FULL_S(" - SGMII port  ");
 623                 DEBUG_INIT_FULL_D_10(sgmii_port, 2);
 624                 DEBUG_INIT_FULL_S("\n");
 625                 reg_write(SGMII_COMPHY_CTRL_REG(sgmii_port), rx_high_imp_mode);
 626                 DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(sgmii_port),
 627                              rx_high_imp_mode);
 628         }                       /* for each serdes lane */
 629
 630         /* Step 6 [PEX-Only] PEX-Main configuration (X4 or X1): */
 631         DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n");
 632         tmp = reg_read(SOC_CTRL_REG);
 633         DEBUG_RD_REG(SOC_CTRL_REG, tmp);
 634         tmp &= 0x200;
 635         if (info->pex_mode[0] == PEX_BUS_MODE_X1)
 636                 tmp |= PCIE0_QUADX1_EN;
 637         if (info->pex_mode[1] == PEX_BUS_MODE_X1)
 638                 tmp |= PCIE1_QUADX1_EN;
 639         if (((reg_read(MPP_SAMPLE_AT_RESET(0)) & PEX_CLK_100MHZ_MASK) >>
 640              PEX_CLK_100MHZ_OFFSET) == 0x1)
 641                 tmp |= (PCIE0_CLK_OUT_EN_MASK | PCIE1_CLK_OUT_EN_MASK);
 642
 643         reg_write(SOC_CTRL_REG, tmp);
 644         DEBUG_WR_REG(SOC_CTRL_REG, tmp);
 645
 646         /* 6.2 PCI Express Link Capabilities */
 647         DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n");
 648
 649         for (line_num = 0; line_num < max_serdes_lines; line_num++) {
 650                 line_cfg = get_line_cfg(line_num, info);
 651
 652                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
 653                         /*
 654                          * PCI Express Control
 655                          * 0xX1A00 [0]:
 656                          * 0x0 X4-Link.
 657                          * 0x1 X1-Link
 658                          */
 659                         pex_unit = line_num >> 2;
 660                         pex_if = MV_SERDES_NUM_TO_PEX_NUM(line_num);
 661                         if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
 662                                 continue;
 663
 664                         /*  set Common Clock Configuration */
 665                         tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
 666                         DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
 667                         tmp |= (1 << 6);
 668                         reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
 669                         DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
 670
 671                         tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
 672                         DEBUG_RD_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
 673                         tmp &= ~(0x3FF);
 674                         if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1)
 675                                 tmp |= (0x1 << 4);
 676                         if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
 677                                 tmp |= (0x4 << 4);
 678                         if (0 == PEX_CAPABILITY_GET(satr11, pex_unit))
 679                                 tmp |= 0x1;
 680                         else
 681                                 tmp |= 0x2;
 682                         DEBUG_INIT_FULL_S("Step 6.2: PEX ");
 683                         DEBUG_INIT_FULL_D(pex_if, 1);
 684                         DEBUG_INIT_FULL_C(" set GEN", (tmp & 3), 1);
 685                         reg_write(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
 686                         DEBUG_WR_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
 687
 688                         /*
 689                          * If pex is X4, no need to pass thru the other
 690                          * 3X1 serdes lines
 691                          */
 692                         if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
 693                                 line_num += 3;
 694                 }
 695         }
 696
 697         /*
 698          * Step 7 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you
 699          * need to config the register SOC_Misc/General Purpose2
 700          * (Address= 182F8)
 701          */
 702         DEBUG_INIT_FULL_S("Step 7: [PEX-X4 Only] To create PEX-Link\n");
 703         tmp = reg_read(GEN_PURP_RES_2_REG);
 704         DEBUG_RD_REG(GEN_PURP_RES_2_REG, tmp);
 705
 706         tmp &= 0xFFFF0000;
 707         if (info->pex_mode[0] == PEX_BUS_MODE_X4)
 708                 tmp |= 0x0000000F;
 709
 710         if (info->pex_mode[1] == PEX_BUS_MODE_X4)
 711                 tmp |= 0x000000F0;
 712
 713         if (info->pex_mode[2] == PEX_BUS_MODE_X4)
 714                 tmp |= 0x00000F00;
 715
 716         if (info->pex_mode[3] == PEX_BUS_MODE_X4)
 717                 tmp |= 0x0000F000;
 718
 719         reg_write(GEN_PURP_RES_2_REG, tmp);
 720         DEBUG_WR_REG(GEN_PURP_RES_2_REG, tmp);
 721
 722         /* Steps  8 , 9 ,10 - use prepared REG addresses and values */
 723         DEBUG_INIT_FULL_S("Steps 7,8,9,10 and 11\n");
 724
 725         /* Prepare PHY parameters for each step according to  MUX selection */
 726         for (line_num = 0; line_num < max_serdes_lines; line_num++) {
 727                 /* for each serdes lane */
 728
 729                 line_cfg = get_line_cfg(line_num, info);
 730
 731                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
 732                         continue;
 733
 734                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
 735                         pex_unit = line_num >> 2;
 736                         pex_line_num = line_num % 4;
 737
 738                         if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
 739                                 continue;
 740                         /*
 741                          * 8)   Configure the desire PHY_MODE (bits [7:5])
 742                          * and REF_FREF_SEL (bits[4:0]) in the register Power
 743                          * and PLL Control (Each MAC contain different Access
 744                          * to reach its Serdes-Regfile).
 745                          */
 746                         if (((info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) &&
 747                              (0 == pex_line_num))
 748                             || ((info->pex_mode[pex_unit] == PEX_BUS_MODE_X1))) {
 749                                 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
 750                                           (0x01 << 16) | (pex_line_num << 24) |
 751                                           0xFC60);
 752                                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
 753                                              (0x01 << 16) | (pex_line_num << 24)
 754                                              | 0xFC60);
 755                                 /*
 756                                  * Step 8.1: [PEX-Only] Configure Max PLL Rate
 757                                  * (bit 8 in  KVCO Calibration Control and
 758                                  * bits[10:9] in
 759                                  */
 760                                 /* Use Maximum PLL Rate(Bit 8) */
 761                                 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
 762                                           (0x02 << 16) | (1 << 31) |
 763                                           (pex_line_num << 24)); /* read command */
 764                                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
 765                                              (0x02 << 16) | (1 << 31) |
 766                                              (pex_line_num << 24));
 767                                 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
 768                                 DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
 769                                 tmp &= ~(1 << 31);
 770                                 tmp |= (1 << 8);
 771                                 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
 772                                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
 773
 774                                 /* Use Maximum PLL Rate(Bits [10:9]) */
 775                                 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
 776                                           (0x81 << 16) | (1 << 31) |
 777                                           (pex_line_num << 24)); /* read command */
 778                                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
 779                                              (0x81 << 16) | (1 << 31) |
 780                                              (pex_line_num << 24));
 781                                 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
 782                                 DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
 783                                 tmp &= ~(1 << 31);
 784                                 tmp |= (3 << 9);
 785                                 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
 786                                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
 787                         }
 788
 789                         continue;
 790                 }
 791
 792                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
 793                         /*
 794                          * Port 0 for serdes lines 4,6,  and port 1 for serdes
 795                          * lines 5
 796                          */
 797                         sata_port = line_num & 1;
 798
 799                         /*
 800                          * 8) Configure the desire PHY_MODE (bits [7:5]) and
 801                          * REF_FREF_SEL (bits[4:0]) in the register Power
 802                          * and PLL Control (Each MAC contain different Access
 803                          * to reach its Serdes-Regfile).
 804                          */
 805                         reg_write(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
 806                         DEBUG_WR_REG(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
 807
 808                         /*  9)  Configure the desire SEL_BITS  */
 809                         reg_write(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
 810                         DEBUG_WR_REG(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
 811
 812                         /* 10)  Configure the desire REFCLK_SEL */
 813
 814                         reg_write(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
 815                         DEBUG_WR_REG(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
 816
 817                         /* 11)  Power up to the PU_PLL,PU_RX,PU_TX.   */
 818                         tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
 819                         DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
 820                         tmp |= 7;
 821                         reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
 822                         DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
 823
 824                         continue;
 825                 }
 826
 827                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
 828                         /*
 829                          * 8)   Configure the desire PHY_MODE (bits [7:5])
 830                          * and REF_FREF_SEL (bits[4:0]) in the register
 831                          */
 832                         reg_write(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
 833                         DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
 834
 835                         /*
 836                          * 9)   Configure the desire SEL_BITS (bits [11:0]
 837                          * in register
 838                          */
 839                         reg_write(SGMII_DIG_LP_ENA_REG(0), 0x400);
 840                         DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(0), 0x400);
 841
 842                         /*
 843                          * 10)  Configure the desire REFCLK_SEL (bit [10])
 844                          * in register
 845                          */
 846                         reg_write(SGMII_REF_CLK_SEL_REG(0), 0x400);
 847                         DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(0), 0x400);
 848
 849                         /* 11)  Power up to the PU_PLL,PU_RX,PU_TX.  */
 850                         tmp = reg_read(SGMII_SERDES_CFG_REG(0));
 851                         DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
 852                         tmp |= 7;
 853                         reg_write(SGMII_SERDES_CFG_REG(0), tmp);
 854                         DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
 855                         continue;
 856                 }
 857
 858                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
 859                         sgmii_port = 0;
 860                 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
 861                         sgmii_port = 1;
 862                 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
 863                         sgmii_port = 2;
 864                 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
 865                         sgmii_port = 3;
 866                 else
 867                         continue;
 868
 869                 /*
 870                  * 8)   Configure the desire PHY_MODE (bits [7:5]) and
 871                  * REF_FREF_SEL (bits[4:0]) in the register
 872                  */
 873                 reg_write(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
 874                 DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
 875
 876                 /* 9)   Configure the desire SEL_BITS (bits [11:0] in register */
 877                 reg_write(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
 878                 DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
 879
 880                 /* 10)  Configure the desire REFCLK_SEL (bit [10]) in register  */
 881                 reg_write(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
 882                 DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
 883
 884                 /* 11)  Power up to the PU_PLL,PU_RX,PU_TX.  */
 885                 tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
 886                 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
 887                 tmp |= 7;
 888                 reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
 889                 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
 890
 891         }                       /* for each serdes lane */
 892
 893         /* Step 12 [PEX-Only] Last phase of PEX-PIPE Configuration */
 894         DEBUG_INIT_FULL_S("Steps 12: [PEX-Only] Last phase of PEX-PIPE Configuration\n");
 895         for (line_num = 0; line_num < max_serdes_lines; line_num++) {
 896                 /* for each serdes lane */
 897
 898                 line_cfg = get_line_cfg(line_num, info);
 899
 900                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
 901                         continue;
 902
 903                 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
 904                         pex_unit = line_num >> 2;
 905                         pex_line_num = line_num % 4;
 906                         if (0 == pex_line_num) {
 907                                 /*
 908                                  * Configure the detection pulse with before
 909                                  * the reset is deasserted
 910                                  */
 911
 912                                 /* Read the old value (indirect access) */
 913                                 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
 914                                           (0x48 << 16) | (1 << 31) |
 915                                           (pex_line_num << 24));
 916                                 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
 917                                 tmp &= ~(1 << 31);      /* Clear read */
 918                                 tmp &= ~(3 << 6);       /* Mask width */
 919                                 /* Insert new detection pulse width */
 920                                 tmp |= serdes_pex_pulse_width[pex_unit] << 6;
 921                                 /* Write value back */
 922                                 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
 923
 924                                 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
 925                                           (0xC1 << 16) | 0x24);
 926                                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
 927                                              (0xC1 << 16) | 0x24);
 928                         }
 929                 }
 930         }
 931
 932         /*--------------------------------------------------------------*/
 933         /* Step 13: Wait 15ms before checking results */
 934         DEBUG_INIT_FULL_S("Steps 13: Wait 15ms before checking results");
 935         mdelay(15);
 936         tmp = 20;
 937         while (tmp) {
 938                 status = MV_OK;
 939                 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
 940                         u32 tmp;
 941                         line_cfg = get_line_cfg(line_num, info);
 942                         if (line_cfg ==
 943                             serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
 944                                 continue;
 945
 946                         if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
 947                                 continue;
 948
 949                         if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
 950                                 /*
 951                                  * Port 0 for serdes lines 4,6,  and port 1
 952                                  * for serdes lines 5
 953                                  */
 954                                 sata_port = line_num & 1;
 955
 956                                 tmp =
 957                                     reg_read(SATA_LP_PHY_EXT_STAT_REG
 958                                              (sata_port));
 959                                 DEBUG_RD_REG(SATA_LP_PHY_EXT_STAT_REG
 960                                              (sata_port), tmp);
 961                                 if ((tmp & 0x7) != 0x7)
 962                                         status = MV_ERROR;
 963                                 continue;
 964                         }
 965
 966                         if (line_cfg ==
 967                             serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
 968                                 tmp = reg_read(SGMII_SERDES_STAT_REG(0));
 969                                 DEBUG_RD_REG(SGMII_SERDES_STAT_REG(0), tmp);
 970                                 if ((tmp & 0x7) != 0x7)
 971                                         status = MV_ERROR;
 972                                 continue;
 973                         }
 974
 975                         if (line_cfg ==
 976                             serdes_cfg[line_num][SERDES_UNIT_SGMII0])
 977                                 sgmii_port = 0;
 978                         else if (line_cfg ==
 979                                  serdes_cfg[line_num][SERDES_UNIT_SGMII1])
 980                                 sgmii_port = 1;
 981                         else if (line_cfg ==
 982                                  serdes_cfg[line_num][SERDES_UNIT_SGMII2])
 983                                 sgmii_port = 2;
 984                         else if (line_cfg ==
 985                                  serdes_cfg[line_num][SERDES_UNIT_SGMII3])
 986                                 sgmii_port = 3;
 987                         else
 988                                 continue;
 989
 990                         tmp = reg_read(SGMII_SERDES_STAT_REG(sgmii_port));
 991                         DEBUG_RD_REG(SGMII_SERDES_STAT_REG(sgmii_port), tmp);
 992                         if ((tmp & 0x7) != 0x7)
 993                                 status = MV_ERROR;
 994                 }
 995
 996                 if (status == MV_OK)
 997                         break;
 998                 mdelay(5);
 999                 tmp--;
1000         }
1001
1002         /*
1003          * Step14 [PEX-Only]  In order to configure RC/EP mode please write
1004          * to register 0x0060 bits
1005          */
1006         DEBUG_INIT_FULL_S("Steps 14: [PEX-Only]  In order to configure\n");
1007         for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
1008                 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
1009                         continue;
1010                 tmp =
1011                     reg_read(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)));
1012                 DEBUG_RD_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
1013                              tmp);
1014                 tmp &= ~(0xf << 20);
1015                 if (info->pex_type == MV_PEX_ROOT_COMPLEX)
1016                         tmp |= (0x4 << 20);
1017                 else
1018                         tmp |= (0x1 << 20);
1019                 reg_write(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
1020                           tmp);
1021                 DEBUG_WR_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
1022                              tmp);
1023         }
1024
1025         /*
1026          * Step 15 [PEX-Only] Only for EP mode set to Zero bits 19 and 16 of
1027          * register 0x1a60
1028          */
1029         DEBUG_INIT_FULL_S("Steps 15: [PEX-Only]  In order to configure\n");
1030         for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
1031                 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
1032                         continue;
1033                 if (info->pex_type == MV_PEX_END_POINT) {
1034                         tmp =
1035                             reg_read(PEX_DBG_CTRL_REG
1036                                      (MV_PEX_UNIT_TO_IF(pex_unit)));
1037                         DEBUG_RD_REG(PEX_DBG_CTRL_REG
1038                                      (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
1039                         tmp &= 0xfff6ffff;
1040                         reg_write(PEX_DBG_CTRL_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
1041                                   tmp);
1042                         DEBUG_WR_REG(PEX_DBG_CTRL_REG
1043                                      (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
1044                 }
1045         }
1046
1047         if (info->serdes_m_phy_change) {
1048                 MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
1049                 u32 bus_speed;
1050                 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
1051                         line_cfg = get_line_cfg(line_num, info);
1052                         if (line_cfg ==
1053                             serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
1054                                 continue;
1055                         serdes_m_phy_change = info->serdes_m_phy_change;
1056                         bus_speed = info->bus_speed & (1 << line_num);
1057                         while (serdes_m_phy_change->type !=
1058                                SERDES_UNIT_UNCONNECTED) {
1059                                 switch (serdes_m_phy_change->type) {
1060                                 case SERDES_UNIT_PEX:
1061                                         if (line_cfg != SERDES_UNIT_PEX)
1062                                                 break;
1063                                         pex_unit = line_num >> 2;
1064                                         pex_line_num = line_num % 4;
1065                                         if (info->pex_mode[pex_unit] ==
1066                                             PEX_BUS_DISABLED)
1067                                                 break;
1068                                         if ((info->pex_mode[pex_unit] ==
1069                                              PEX_BUS_MODE_X4) && pex_line_num)
1070                                                 break;
1071
1072                                         if (bus_speed) {
1073                                                 reg_write(PEX_PHY_ACCESS_REG
1074                                                           (pex_unit),
1075                                                           (pex_line_num << 24) |
1076                                                           serdes_m_phy_change->val_hi_speed);
1077                                                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG
1078                                                              (pex_unit),
1079                                                              (pex_line_num <<
1080                                                               24) |
1081                                                              serdes_m_phy_change->val_hi_speed);
1082                                         } else {
1083                                                 reg_write(PEX_PHY_ACCESS_REG
1084                                                           (pex_unit),
1085                                                           (pex_line_num << 24) |
1086                                                           serdes_m_phy_change->val_low_speed);
1087                                                 DEBUG_WR_REG(PEX_PHY_ACCESS_REG
1088                                                              (pex_unit),
1089                                                              (pex_line_num <<
1090                                                               24) |
1091                                                              serdes_m_phy_change->val_low_speed);
1092                                         }
1093                                         break;
1094                                 case SERDES_UNIT_SATA:
1095                                         if (line_cfg != SERDES_UNIT_SATA)
1096                                                 break;
1097                                         /*
1098                                          * Port 0 for serdes lines 4,6,  and
1099                                          * port 1 for serdes lines 5
1100                                          */
1101                                         sata_port = line_num & 1;
1102                                         if (bus_speed) {
1103                                                 reg_write(SATA_BASE_REG
1104                                                           (sata_port) |
1105                                                           serdes_m_phy_change->reg_hi_speed,
1106                                                           serdes_m_phy_change->val_hi_speed);
1107                                                 DEBUG_WR_REG(SATA_BASE_REG
1108                                                              (sata_port) |
1109                                                              serdes_m_phy_change->reg_hi_speed,
1110                                                              serdes_m_phy_change->val_hi_speed);
1111                                         } else {
1112                                                 reg_write(SATA_BASE_REG
1113                                                           (sata_port) |
1114                                                           serdes_m_phy_change->reg_low_speed,
1115                                                           serdes_m_phy_change->val_low_speed);
1116                                                 DEBUG_WR_REG(SATA_BASE_REG
1117                                                              (sata_port) |
1118                                                              serdes_m_phy_change->reg_low_speed,
1119                                                              serdes_m_phy_change->val_low_speed);
1120                                         }
1121                                         break;
1122                                 case SERDES_UNIT_SGMII0:
1123                                 case SERDES_UNIT_SGMII1:
1124                                 case SERDES_UNIT_SGMII2:
1125                                 case SERDES_UNIT_SGMII3:
1126                                         if (line_cfg == serdes_cfg[line_num]
1127                                             [SERDES_UNIT_SGMII0])
1128                                                 sgmii_port = 0;
1129                                         else if (line_cfg ==
1130                                                  serdes_cfg[line_num]
1131                                                  [SERDES_UNIT_SGMII1])
1132                                                 sgmii_port = 1;
1133                                         else if (line_cfg ==
1134                                                  serdes_cfg[line_num]
1135                                                  [SERDES_UNIT_SGMII2])
1136                                                 sgmii_port = 2;
1137                                         else if (line_cfg ==
1138                                                  serdes_cfg[line_num]
1139                                                  [SERDES_UNIT_SGMII3])
1140                                                 sgmii_port = 3;
1141                                         else
1142                                                 break;
1143                                         if (bus_speed) {
1144                                                 reg_write(MV_ETH_REGS_BASE
1145                                                           (sgmii_port) |
1146                                                           serdes_m_phy_change->reg_hi_speed,
1147                                                           serdes_m_phy_change->val_hi_speed);
1148                                                 DEBUG_WR_REG(MV_ETH_REGS_BASE
1149                                                              (sgmii_port) |
1150                                                              serdes_m_phy_change->reg_hi_speed,
1151                                                              serdes_m_phy_change->val_hi_speed);
1152                                         } else {
1153                                                 reg_write(MV_ETH_REGS_BASE
1154                                                           (sgmii_port) |
1155                                                           serdes_m_phy_change->reg_low_speed,
1156                                                           serdes_m_phy_change->val_low_speed);
1157                                                 DEBUG_WR_REG(MV_ETH_REGS_BASE
1158                                                              (sgmii_port) |
1159                                                              serdes_m_phy_change->reg_low_speed,
1160                                                              serdes_m_phy_change->val_low_speed);
1161                                         }
1162                                         break;
1163                                 case SERDES_UNIT_QSGMII:
1164                                         if (line_cfg != SERDES_UNIT_QSGMII)
1165                                                 break;
1166                                         if (bus_speed) {
1167                                                 reg_write
1168                                                     (serdes_m_phy_change->reg_hi_speed,
1169                                                      serdes_m_phy_change->val_hi_speed);
1170                                                 DEBUG_WR_REG
1171                                                     (serdes_m_phy_change->reg_hi_speed,
1172                                                      serdes_m_phy_change->val_hi_speed);
1173                                         } else {
1174                                                 reg_write
1175                                                     (serdes_m_phy_change->reg_low_speed,
1176                                                      serdes_m_phy_change->val_low_speed);
1177                                                 DEBUG_WR_REG
1178                                                     (serdes_m_phy_change->reg_low_speed,
1179                                                      serdes_m_phy_change->val_low_speed);
1180                                         }
1181                                         break;
1182                                 default:
1183                                         break;
1184                                 }
1185                                 serdes_m_phy_change++;
1186                         }
1187                 }
1188         }
1189
1190         /* Step 16 [PEX-Only] Training Enable */
1191         DEBUG_INIT_FULL_S("Steps 16: [PEX-Only] Training Enable");
1192         tmp = reg_read(SOC_CTRL_REG);
1193         DEBUG_RD_REG(SOC_CTRL_REG, tmp);
1194         tmp &= ~(0x0F);
1195         for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
1196                 reg_write(PEX_CAUSE_REG(pex_unit), 0);
1197                 DEBUG_WR_REG(PEX_CAUSE_REG(pex_unit), 0);
1198                 if (info->pex_mode[pex_unit] != PEX_BUS_DISABLED)
1199                         tmp |= (0x1 << pex_unit);
1200         }
1201         reg_write(SOC_CTRL_REG, tmp);
1202         DEBUG_WR_REG(SOC_CTRL_REG, tmp);
1203
1204         /* Step 17: Speed change to target speed and width */
1205         {
1206                 u32 tmp_reg, tmp_pex_reg;
1207                 u32 addr;
1208                 u32 first_busno, next_busno;
1209                 u32 max_link_width = 0;
1210                 u32 neg_link_width = 0;
1211                 pex_if_num = pex_max_if_get();
1212                 mdelay(150);
1213                 DEBUG_INIT_FULL_C("step 17: max_if= 0x", pex_if_num, 1);
1214                 next_busno = 0;
1215                 for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
1216                         line_num = (pex_if <= 8) ? pex_if : 12;
1217                         line_cfg = get_line_cfg(line_num, info);
1218                         if (line_cfg != serdes_cfg[line_num][SERDES_UNIT_PEX])
1219                                 continue;
1220                         pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
1221                         DEBUG_INIT_FULL_S("step 17:  PEX");
1222                         DEBUG_INIT_FULL_D(pex_if, 1);
1223                         DEBUG_INIT_FULL_C("  pex_unit= ", pex_unit, 1);
1224
1225                         if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
1226                                 DEBUG_INIT_FULL_C("PEX disabled interface ",
1227                                                   pex_if, 1);
1228                                 if (pex_if < 8)
1229                                         pex_if += 3;
1230                                 continue;
1231                         }
1232                         first_busno = next_busno;
1233                         if ((info->pex_type == MV_PEX_END_POINT) &&
1234                             (0 == pex_if)) {
1235                                 if ((pex_if < 8) && (info->pex_mode[pex_unit] ==
1236                                                      PEX_BUS_MODE_X4))
1237                                         pex_if += 3;
1238                                 continue;
1239                         }
1240
1241                         tmp = reg_read(PEX_DBG_STATUS_REG(pex_if));
1242                         DEBUG_RD_REG(PEX_DBG_STATUS_REG(pex_if), tmp);
1243                         if ((tmp & 0x7f) == 0x7e) {
1244                                 next_busno++;
1245                                 tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
1246                                 max_link_width = tmp;
1247                                 DEBUG_RD_REG((PEX_LINK_CAPABILITIES_REG
1248                                               (pex_if)), tmp);
1249                                 max_link_width = ((max_link_width >> 4) & 0x3F);
1250                                 neg_link_width =
1251                                     reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
1252                                 DEBUG_RD_REG((PEX_LINK_CTRL_STATUS_REG(pex_if)),
1253                                              neg_link_width);
1254                                 neg_link_width = ((neg_link_width >> 20) & 0x3F);
1255                                 if (max_link_width > neg_link_width) {
1256                                         tmp &= ~(0x3F << 4);
1257                                         tmp |= (neg_link_width << 4);
1258                                         reg_write(PEX_LINK_CAPABILITIES_REG
1259                                                   (pex_if), tmp);
1260                                         DEBUG_WR_REG((PEX_LINK_CAPABILITIES_REG
1261                                                       (pex_if)), tmp);
1262                                         mdelay(1);      /* wait 1ms before reading  capability for speed */
1263                                         DEBUG_INIT_S("PEX");
1264                                         DEBUG_INIT_D(pex_if, 1);
1265                                         DEBUG_INIT_C(": change width to X",
1266                                                      neg_link_width, 1);
1267                                 }
1268                                 tmp_pex_reg =
1269                                     reg_read((PEX_CFG_DIRECT_ACCESS
1270                                               (pex_if,
1271                                                PEX_LINK_CAPABILITY_REG)));
1272                                 DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS
1273                                               (pex_if,
1274                                                PEX_LINK_CAPABILITY_REG)),
1275                                              tmp_pex_reg);
1276                                 tmp_pex_reg &= (0xF);
1277                                 if (tmp_pex_reg == 0x2) {
1278                                         tmp_reg =
1279                                             (reg_read
1280                                              (PEX_CFG_DIRECT_ACCESS
1281                                               (pex_if,
1282                                                PEX_LINK_CTRL_STAT_REG)) &
1283                                              0xF0000) >> 16;
1284                                         DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS
1285                                                      (pex_if,
1286                                                       PEX_LINK_CTRL_STAT_REG),
1287                                                      tmp_pex_reg);
1288                                         /* check if the link established is GEN1 */
1289                                         if (tmp_reg == 0x1) {
1290                                                 pex_local_bus_num_set(pex_if,
1291                                                                       first_busno);
1292                                                 pex_local_dev_num_set(pex_if,
1293                                                                       1);
1294
1295                                                 DEBUG_INIT_FULL_S("** Link is Gen1, check the EP capability\n");
1296                                                 /* link is Gen1, check the EP capability */
1297                                                 addr =
1298                                                     pex_cfg_read(pex_if,
1299                                                                  first_busno, 0,
1300                                                                  0,
1301                                                                  0x34) & 0xFF;
1302                                                 DEBUG_INIT_FULL_C("pex_cfg_read: return addr=0x%x",
1303                                                      addr, 4);
1304                                                 if (addr == 0xff) {
1305                                                         DEBUG_INIT_FULL_C("pex_cfg_read: return 0xff -->PEX (%d): Detected No Link.",
1306                                                                           pex_if, 1);
1307                                                         continue;
1308                                                 }
1309                                                 while ((pex_cfg_read
1310                                                         (pex_if, first_busno, 0,
1311                                                          0,
1312                                                          addr) & 0xFF) !=
1313                                                        0x10) {
1314                                                         addr =
1315                                                             (pex_cfg_read
1316                                                              (pex_if,
1317                                                               first_busno, 0, 0,
1318                                                               addr) & 0xFF00) >>
1319                                                             8;
1320                                                 }
1321                                                 if ((pex_cfg_read
1322                                                      (pex_if, first_busno, 0, 0,
1323                                                       addr + 0xC) & 0xF) >=
1324                                                     0x2) {
1325                                                         tmp =
1326                                                             reg_read
1327                                                             (PEX_LINK_CTRL_STATUS2_REG
1328                                                              (pex_if));
1329                                                         DEBUG_RD_REG
1330                                                             (PEX_LINK_CTRL_STATUS2_REG
1331                                                              (pex_if), tmp);
1332                                                         tmp &= ~(0x1 | 1 << 1);
1333                                                         tmp |= (1 << 1);
1334                                                         reg_write
1335                                                             (PEX_LINK_CTRL_STATUS2_REG
1336                                                              (pex_if), tmp);
1337                                                         DEBUG_WR_REG
1338                                                             (PEX_LINK_CTRL_STATUS2_REG
1339                                                              (pex_if), tmp);
1340
1341                                                         tmp =
1342                                                             reg_read
1343                                                             (PEX_CTRL_REG
1344                                                              (pex_if));
1345                                                         DEBUG_RD_REG
1346                                                             (PEX_CTRL_REG
1347                                                              (pex_if), tmp);
1348                                                         tmp |= (1 << 10);
1349                                                         reg_write(PEX_CTRL_REG
1350                                                                   (pex_if),
1351                                                                   tmp);
1352                                                         DEBUG_WR_REG
1353                                                             (PEX_CTRL_REG
1354                                                              (pex_if), tmp);
1355                                                         mdelay(10);     /* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state */
1356                                                         DEBUG_INIT_FULL_S
1357                                                             ("Gen2 client!\n");
1358                                                 } else {
1359                                                         DEBUG_INIT_FULL_S
1360                                                             ("GEN1 client!\n");
1361                                                 }
1362                                         }
1363                                 }
1364                         } else {
1365                                 DEBUG_INIT_FULL_S("PEX");
1366                                 DEBUG_INIT_FULL_D(pex_if, 1);
1367                                 DEBUG_INIT_FULL_S(" : Detected No Link. Status Reg(0x");
1368                                 DEBUG_INIT_FULL_D(PEX_DBG_STATUS_REG(pex_if),
1369                                                   8);
1370                                 DEBUG_INIT_FULL_C(") = 0x", tmp, 8);
1371                         }
1372
1373                         if ((pex_if < 8) &&
1374                             (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1375                                 pex_if += 3;
1376                 }
1377         }
1378
1379         /* Step 18: update pex DEVICE ID */
1380         {
1381                 u32 devId;
1382                 pex_if_num = pex_max_if_get();
1383                 ctrl_mode = ctrl_model_get();
1384                 for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
1385                         pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
1386                         if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
1387                                 if ((pex_if < 8) &&
1388                                     (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1389                                         pex_if += 3;
1390                                 continue;
1391                         }
1392
1393                         devId = reg_read(PEX_CFG_DIRECT_ACCESS(
1394                                                  pex_if, PEX_DEVICE_AND_VENDOR_ID));
1395                         devId &= 0xFFFF;
1396                         devId |= ((ctrl_mode << 16) & 0xffff0000);
1397                         DEBUG_INIT_FULL_S("Update Device ID PEX");
1398                         DEBUG_INIT_FULL_D(pex_if, 1);
1399                         DEBUG_INIT_FULL_D(devId, 8);
1400                         DEBUG_INIT_FULL_S("\n");
1401                         reg_write(PEX_CFG_DIRECT_ACCESS
1402                                   (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
1403                         if ((pex_if < 8) &&
1404                             (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1405                                 pex_if += 3;
1406                 }
1407                 DEBUG_INIT_FULL_S("Update PEX Device ID 0x");
1408                 DEBUG_INIT_FULL_D(ctrl_mode, 4);
1409                 DEBUG_INIT_FULL_S("0\n");
1410         }
1411         tmp = reg_read(PEX_DBG_STATUS_REG(0));
1412         DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
1413
1414         DEBUG_INIT_S(ENDED_OK);
1415         return MV_OK;
1416 }
1417
1418 /* PEX configuration space read write */
1419
1420 /*
1421  * pex_cfg_read - Read from configuration space
1422  *
1423  * DESCRIPTION:
1424  *       This function performs a 32 bit read from PEX configuration space.
1425  *       It supports both type 0 and type 1 of Configuration Transactions
1426  *       (local and over bridge). In order to read from local bus segment, use
1427  *       bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers
1428  *       will result configuration transaction of type 1 (over bridge).
1429  *
1430  * INPUT:
1431  *       pex_if   - PEX interface number.
1432  *       bus     - PEX segment bus number.
1433  *       dev     - PEX device number.
1434  *       func    - Function number.
1435  *       offss - Register offset.
1436  *
1437  * OUTPUT:
1438  *       None.
1439  *
1440  * RETURN:
1441  *       32bit register data, 0xffffffff on error
1442  *
1443  */
1444 u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs)
1445 {
1446         u32 pex_data = 0;
1447         u32 local_dev, local_bus;
1448         u32 val;
1449
1450         if (pex_if >= MV_PEX_MAX_IF)
1451                 return 0xFFFFFFFF;
1452
1453         if (dev >= MAX_PEX_DEVICES) {
1454                 DEBUG_INIT_C("pex_cfg_read: ERR. device number illigal ", dev,
1455                              1);
1456                 return 0xFFFFFFFF;
1457         }
1458
1459         if (func >= MAX_PEX_FUNCS) {
1460                 DEBUG_INIT_C("pex_cfg_read: ERR. function num illigal ", func,
1461                              1);
1462                 return 0xFFFFFFFF;
1463         }
1464
1465         if (bus >= MAX_PEX_BUSSES) {
1466                 DEBUG_INIT_C("pex_cfg_read: ERR. bus number illigal ", bus, 1);
1467                 return MV_ERROR;
1468         }
1469         val = reg_read(PEX_STATUS_REG(pex_if));
1470
1471         local_dev =
1472             ((val & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
1473         local_bus =
1474             ((val & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
1475
1476         /* Speed up the process. In case on no link, return MV_ERROR */
1477         if ((dev != local_dev) || (bus != local_bus)) {
1478                 pex_data = reg_read(PEX_STATUS_REG(pex_if));
1479
1480                 if ((pex_data & PXSR_DL_DOWN))
1481                         return MV_ERROR;
1482         }
1483
1484         /*
1485          * In PCI Express we have only one device number
1486          * and this number is the first number we encounter else that the
1487          * local_dev spec pex define return on config read/write on any device
1488          */
1489         if (bus == local_bus) {
1490                 if (local_dev == 0) {
1491                         /*
1492                          * If local dev is 0 then the first number we encounter
1493                          * after 0 is 1
1494                          */
1495                         if ((dev != 1) && (dev != local_dev))
1496                                 return MV_ERROR;
1497                 } else {
1498                         /*
1499                          * If local dev is not 0 then the first number we
1500                          * encounter is 0
1501                          */
1502                         if ((dev != 0) && (dev != local_dev))
1503                                 return MV_ERROR;
1504                 }
1505         }
1506
1507         /* Creating PEX address to be passed */
1508         pex_data = (bus << PXCAR_BUS_NUM_OFFS);
1509         pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
1510         pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
1511         pex_data |= (offs & PXCAR_REG_NUM_MASK);        /* lgacy register space */
1512         /* extended register space */
1513         pex_data |= (((offs & PXCAR_REAL_EXT_REG_NUM_MASK) >>
1514                      PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
1515
1516         pex_data |= PXCAR_CONFIG_EN;
1517
1518         /* Write the address to the PEX configuration address register */
1519         reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
1520
1521         /*
1522          * In order to let the PEX controller absorbed the address of the read
1523          * transaction we perform a validity check that the address was written
1524          */
1525         if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
1526                 return MV_ERROR;
1527
1528         /* cleaning Master Abort */
1529         reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
1530                     PXSAC_MABORT);
1531         /* Read the Data returned in the PEX Data register */
1532         pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
1533
1534         DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
1535
1536         return pex_data;
1537 }
1538
1539 /*
1540  * pex_local_bus_num_set - Set PEX interface local bus number.
1541  *
1542  * DESCRIPTION:
1543  *       This function sets given PEX interface its local bus number.
1544  *       Note: In case the PEX interface is PEX-X, the information is read-only.
1545  *
1546  * INPUT:
1547  *       pex_if  - PEX interface number.
1548  *       bus_num - Bus number.
1549  *
1550  * OUTPUT:
1551  *       None.
1552  *
1553  * RETURN:
1554  *       MV_NOT_ALLOWED in case PEX interface is PEX-X.
1555  *              MV_BAD_PARAM on bad parameters ,
1556  *       otherwise MV_OK
1557  *
1558  */
1559 int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
1560 {
1561         u32 val;
1562
1563         if (bus_num >= MAX_PEX_BUSSES) {
1564                 DEBUG_INIT_C("pex_local_bus_num_set: ERR. bus number illigal %d\n",
1565                      bus_num, 4);
1566                 return MV_ERROR;
1567         }
1568
1569         val = reg_read(PEX_STATUS_REG(pex_if));
1570         val &= ~PXSR_PEX_BUS_NUM_MASK;
1571         val |= (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
1572         reg_write(PEX_STATUS_REG(pex_if), val);
1573
1574         return MV_OK;
1575 }
1576
1577 /*
1578  * pex_local_dev_num_set - Set PEX interface local device number.
1579  *
1580  * DESCRIPTION:
1581  *       This function sets given PEX interface its local device number.
1582  *       Note: In case the PEX interface is PEX-X, the information is read-only.
1583  *
1584  * INPUT:
1585  *       pex_if  - PEX interface number.
1586  *       dev_num - Device number.
1587  *
1588  * OUTPUT:
1589  *       None.
1590  *
1591  * RETURN:
1592  *       MV_NOT_ALLOWED in case PEX interface is PEX-X.
1593  *              MV_BAD_PARAM on bad parameters ,
1594  *       otherwise MV_OK
1595  *
1596  */
1597 int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
1598 {
1599         u32 val;
1600
1601         if (pex_if >= MV_PEX_MAX_IF)
1602                 return MV_BAD_PARAM;
1603
1604         val = reg_read(PEX_STATUS_REG(pex_if));
1605         val &= ~PXSR_PEX_DEV_NUM_MASK;
1606         val |= (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
1607         reg_write(PEX_STATUS_REG(pex_if), val);
1608
1609         return MV_OK;
1610 }