arch/arm/mach-k3/include/mach/am6_hardware.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * K3: AM6 SoC definitions, structures etc.
   4  *
   5  * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7 #ifndef __ASM_ARCH_AM6_HARDWARE_H
   8 #define __ASM_ARCH_AM6_HARDWARE_H
   9
  10 #include <config.h>
  11
  12 #define CTRL_MMR0_BASE                                  0x00100000
  13 #define CTRLMMR_MAIN_DEVSTAT                            (CTRL_MMR0_BASE + 0x30)
  14
  15 #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK              GENMASK(3, 0)
  16 #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT             0
  17 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK         GENMASK(6, 4)
  18 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT        4
  19
  20 #define WKUP_CTRL_MMR0_BASE                             0x43000000
  21 #define MCU_CTRL_MMR0_BASE                              0x40f00000
  22
  23 /*
  24  * The CTRL_MMR0 memory space is divided into several equally-spaced
  25  * partitions, so defining the partition size allows us to determine
  26  * register addresses common to those partitions.
  27  */
  28 #define CTRL_MMR0_PARTITION_SIZE                        0x4000
  29
  30 /*
  31  * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
  32  * shared register definitions.
  33  */
  34 #define CTRLMMR_LOCK_KICK0                              0x01008
  35 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL                   0x68ef3490
  36 #define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK                BIT(0)
  37 #define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT               0
  38 #define CTRLMMR_LOCK_KICK1                              0x0100c
  39 #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL                   0xd172bc5a
  40
  41 /* MCU SCRATCHPAD usage */
  42 #define K3_BOOT_PARAM_TABLE_INDEX_VAL   CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
  43
  44 #endif /* __ASM_ARCH_AM6_HARDWARE_H */