1 // SPDX-License-Identifier: GPL-2.0+
3 * AM6: SoC specific initialization
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/sysfw-loader.h>
14 #include <asm/arch/sys_proto.h>
17 #include <dm/uclass-internal.h>
18 #include <dm/pinctrl.h>
19 #include <linux/soc/ti/ti_sci_protocol.h>
22 #ifdef CONFIG_SPL_BUILD
23 #ifdef CONFIG_K3_LOAD_SYSFW
24 #ifdef CONFIG_TI_SECURE_DEVICE
25 struct fwl_data main_cbass_fwls[] = {
26 { "MMCSD1_CFG", 2057, 1 },
27 { "MMCSD0_CFG", 2058, 1 },
28 { "USB3SS0_SLV0", 2176, 2 },
29 { "PCIE0_SLV", 2336, 8 },
30 { "PCIE1_SLV", 2337, 8 },
31 { "PCIE0_CFG", 2688, 1 },
32 { "PCIE1_CFG", 2689, 1 },
33 }, mcu_cbass_fwls[] = {
34 { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
35 { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
36 { "MCU_FSS0_S1", 1033, 8 },
37 { "MCU_FSS0_S0", 1036, 8 },
38 { "MCU_CPSW0", 1220, 1 },
43 static void mmr_unlock(u32 base, u32 partition)
45 /* Translate the base address */
46 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
48 /* Unlock the requested partition if locked using two-step sequence */
49 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
50 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
53 static void ctrl_mmr_unlock(void)
55 /* Unlock all WKUP_CTRL_MMR0 module registers */
56 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
57 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
58 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
59 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
60 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
61 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
63 /* Unlock all MCU_CTRL_MMR0 module registers */
64 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
65 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
66 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
67 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
69 /* Unlock all CTRL_MMR0 module registers */
70 mmr_unlock(CTRL_MMR0_BASE, 0);
71 mmr_unlock(CTRL_MMR0_BASE, 1);
72 mmr_unlock(CTRL_MMR0_BASE, 2);
73 mmr_unlock(CTRL_MMR0_BASE, 3);
74 mmr_unlock(CTRL_MMR0_BASE, 6);
75 mmr_unlock(CTRL_MMR0_BASE, 7);
79 * This uninitialized global variable would normal end up in the .bss section,
80 * but the .bss is cleared between writing and reading this variable, so move
81 * it to the .data section.
83 u32 bootindex __attribute__((section(".data")));
85 static void store_boot_index_from_rom(void)
87 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
90 #if defined(CONFIG_K3_LOAD_SYSFW)
91 void k3_mmc_stop_clock(void)
93 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
94 struct mmc *mmc = find_mmc_device(0);
99 mmc->saved_clock = mmc->clock;
100 mmc_set_clock(mmc, 0, true);
104 void k3_mmc_restart_clock(void)
106 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
107 struct mmc *mmc = find_mmc_device(0);
112 mmc_set_clock(mmc, mmc->saved_clock, false);
117 void board_init_f(ulong dummy)
119 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
124 * Cannot delay this further as there is a chance that
125 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
127 store_boot_index_from_rom();
129 /* Make all control module registers accessible */
132 #ifdef CONFIG_CPU_V7R
133 disable_linefill_optimization();
134 setup_k3_mpu_regions();
137 /* Init DM early in-order to invoke system controller */
140 #ifdef CONFIG_K3_EARLY_CONS
142 * Allow establishing an early console as required for example when
143 * doing a UART-based boot. Note that this console may not "survive"
144 * through a SYSFW PM-init step and will need a re-init in some way
145 * due to changing module clock frequencies.
147 early_console_init();
150 #ifdef CONFIG_K3_LOAD_SYSFW
152 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
153 * regardless of the result of pinctrl. Do this without probing the
154 * device, but instead by searching the device that would request the
155 * given sequence number if probed. The UART will be used by the system
156 * firmware (SYSFW) image for various purposes and SYSFW depends on us
157 * to initialize its pin settings.
159 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
161 pinctrl_select_state(dev, "default");
164 * Load, start up, and configure system controller firmware. Provide
165 * the U-Boot console init function to the SYSFW post-PM configuration
166 * callback hook, effectively switching on (or over) the console
169 k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
171 /* Prepare console output */
172 preloader_console_init();
174 /* Disable ROM configured firewalls right after loading sysfw */
175 #ifdef CONFIG_TI_SECURE_DEVICE
176 remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
177 remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
180 /* Prepare console output */
181 preloader_console_init();
184 /* Perform EEPROM-based board detection */
187 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
188 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
191 printf("AVS init failed: %d\n", ret);
194 #ifdef CONFIG_K3_AM654_DDRSS
195 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
197 panic("DRAM init failed: %d\n", ret);
201 u32 spl_boot_mode(const u32 boot_device)
203 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
204 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
206 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
207 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
209 /* eMMC boot0 mode is only supported for primary boot */
210 if (bootindex == K3_PRIMARY_BOOTMODE &&
211 bootmode == BOOT_DEVICE_MMC1)
212 return MMCSD_MODE_EMMCBOOT;
215 /* Everything else use filesystem if available */
216 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
217 return MMCSD_MODE_FS;
219 return MMCSD_MODE_RAW;
223 static u32 __get_backup_bootmedia(u32 devstat)
225 u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
226 CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
229 case BACKUP_BOOT_DEVICE_USB:
230 return BOOT_DEVICE_USB;
231 case BACKUP_BOOT_DEVICE_UART:
232 return BOOT_DEVICE_UART;
233 case BACKUP_BOOT_DEVICE_ETHERNET:
234 return BOOT_DEVICE_ETHERNET;
235 case BACKUP_BOOT_DEVICE_MMC2:
237 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
238 CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
240 return BOOT_DEVICE_MMC1;
241 return BOOT_DEVICE_MMC2;
243 case BACKUP_BOOT_DEVICE_SPI:
244 return BOOT_DEVICE_SPI;
245 case BACKUP_BOOT_DEVICE_HYPERFLASH:
246 return BOOT_DEVICE_HYPERFLASH;
247 case BACKUP_BOOT_DEVICE_I2C:
248 return BOOT_DEVICE_I2C;
251 return BOOT_DEVICE_RAM;
254 static u32 __get_primary_bootmedia(u32 devstat)
256 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
257 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
259 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
260 bootmode = BOOT_DEVICE_SPI;
262 if (bootmode == BOOT_DEVICE_MMC2) {
263 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
264 CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
266 bootmode = BOOT_DEVICE_MMC1;
267 } else if (bootmode == BOOT_DEVICE_MMC1) {
268 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
269 CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
271 bootmode = BOOT_DEVICE_MMC2;
277 u32 spl_boot_device(void)
279 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
281 if (bootindex == K3_PRIMARY_BOOTMODE)
282 return __get_primary_bootmedia(devstat);
284 return __get_backup_bootmedia(devstat);
288 #ifdef CONFIG_SYS_K3_SPL_ATF
290 #define AM6_DEV_MCU_RTI0 134
291 #define AM6_DEV_MCU_RTI1 135
292 #define AM6_DEV_MCU_ARMSS0_CPU0 159
293 #define AM6_DEV_MCU_ARMSS0_CPU1 245
295 void release_resources_for_core_shutdown(void)
297 struct ti_sci_handle *ti_sci = get_ti_sci_handle();
298 struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
299 struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
303 const u32 put_device_ids[] = {
308 /* Iterate through list of devices to put (shutdown) */
309 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
310 u32 id = put_device_ids[i];
312 ret = dev_ops->put_device(ti_sci, id);
314 panic("Failed to put device %u (%d)\n", id, ret);
317 const u32 put_core_ids[] = {
318 AM6_DEV_MCU_ARMSS0_CPU1,
319 AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
322 /* Iterate through list of cores to put (shutdown) */
323 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
324 u32 id = put_core_ids[i];
327 * Queue up the core shutdown request. Note that this call
328 * needs to be followed up by an actual invocation of an WFE
329 * or WFI CPU instruction.
331 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
333 panic("Failed sending core %u shutdown message (%d)\n",