1 // SPDX-License-Identifier: GPL-2.0+
3 * K3: Architecture initialization
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/sysfw-loader.h>
16 #include <dm/uclass-internal.h>
17 #include <dm/pinctrl.h>
19 #ifdef CONFIG_SPL_BUILD
20 static void mmr_unlock(u32 base, u32 partition)
22 /* Translate the base address */
23 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
25 /* Unlock the requested partition if locked using two-step sequence */
26 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
27 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
30 static void ctrl_mmr_unlock(void)
32 /* Unlock all WKUP_CTRL_MMR0 module registers */
33 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
34 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
35 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
36 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
37 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
38 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
40 /* Unlock all MCU_CTRL_MMR0 module registers */
41 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
42 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
43 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
44 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
46 /* Unlock all CTRL_MMR0 module registers */
47 mmr_unlock(CTRL_MMR0_BASE, 0);
48 mmr_unlock(CTRL_MMR0_BASE, 1);
49 mmr_unlock(CTRL_MMR0_BASE, 2);
50 mmr_unlock(CTRL_MMR0_BASE, 3);
51 mmr_unlock(CTRL_MMR0_BASE, 6);
52 mmr_unlock(CTRL_MMR0_BASE, 7);
56 * This uninitialized global variable would normal end up in the .bss section,
57 * but the .bss is cleared between writing and reading this variable, so move
58 * it to the .data section.
60 u32 bootindex __attribute__((section(".data")));
62 static void store_boot_index_from_rom(void)
64 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
67 void board_init_f(ulong dummy)
69 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
74 * Cannot delay this further as there is a chance that
75 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
77 store_boot_index_from_rom();
79 /* Make all control module registers accessible */
83 setup_k3_mpu_regions();
86 /* Init DM early in-order to invoke system controller */
89 #ifdef CONFIG_K3_LOAD_SYSFW
91 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
92 * regardless of the result of pinctrl. Do this without probing the
93 * device, but instead by searching the device that would request the
94 * given sequence number if probed. The UART will be used by the system
95 * firmware (SYSFW) image for various purposes and SYSFW depends on us
96 * to initialize its pin settings.
98 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
100 pinctrl_select_state(dev, "default");
103 * Load, start up, and configure system controller firmware. Provide
104 * the U-Boot console init function to the SYSFW post-PM configuration
105 * callback hook, effectively switching on (or over) the console
108 k3_sysfw_loader(preloader_console_init);
110 /* Prepare console output */
111 preloader_console_init();
114 #ifdef CONFIG_K3_AM654_DDRSS
115 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
117 panic("DRAM init failed: %d\n", ret);
121 u32 spl_boot_mode(const u32 boot_device)
123 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
124 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
126 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
127 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
129 /* eMMC boot0 mode is only supported for primary boot */
130 if (bootindex == K3_PRIMARY_BOOTMODE &&
131 bootmode == BOOT_DEVICE_MMC1)
132 return MMCSD_MODE_EMMCBOOT;
135 /* Everything else use filesystem if available */
136 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
137 return MMCSD_MODE_FS;
139 return MMCSD_MODE_RAW;
143 static u32 __get_backup_bootmedia(u32 devstat)
145 u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
146 CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
149 case BACKUP_BOOT_DEVICE_USB:
150 return BOOT_DEVICE_USB;
151 case BACKUP_BOOT_DEVICE_UART:
152 return BOOT_DEVICE_UART;
153 case BACKUP_BOOT_DEVICE_ETHERNET:
154 return BOOT_DEVICE_ETHERNET;
155 case BACKUP_BOOT_DEVICE_MMC2:
157 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
158 CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
160 return BOOT_DEVICE_MMC1;
161 return BOOT_DEVICE_MMC2;
163 case BACKUP_BOOT_DEVICE_SPI:
164 return BOOT_DEVICE_SPI;
165 case BACKUP_BOOT_DEVICE_HYPERFLASH:
166 return BOOT_DEVICE_HYPERFLASH;
167 case BACKUP_BOOT_DEVICE_I2C:
168 return BOOT_DEVICE_I2C;
171 return BOOT_DEVICE_RAM;
174 static u32 __get_primary_bootmedia(u32 devstat)
176 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
177 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
179 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
180 bootmode = BOOT_DEVICE_SPI;
182 if (bootmode == BOOT_DEVICE_MMC2) {
183 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
184 CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
186 bootmode = BOOT_DEVICE_MMC1;
187 } else if (bootmode == BOOT_DEVICE_MMC1) {
188 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
189 CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
191 bootmode = BOOT_DEVICE_MMC2;
197 u32 spl_boot_device(void)
199 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
201 if (bootindex == K3_PRIMARY_BOOTMODE)
202 return __get_primary_bootmedia(devstat);
204 return __get_backup_bootmedia(devstat);
208 #ifndef CONFIG_SYSRESET
209 void reset_cpu(ulong ignored)