arch/arm/mach-k3/am6_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * K3: Architecture initialization
   4  *
   5  * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <spl.h>
  12 #include <asm/arch/hardware.h>
  13
  14 #ifdef CONFIG_SPL_BUILD
  15 static void mmr_unlock(u32 base, u32 partition)
  16 {
  17         /* Translate the base address */
  18         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  19
  20         /* Unlock the requested partition if locked using two-step sequence */
  21         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  22         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  23 }
  24
  25 static void ctrl_mmr_unlock(void)
  26 {
  27         /* Unlock all WKUP_CTRL_MMR0 module registers */
  28         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  29         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  30         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  31         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  32         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  33         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  34
  35         /* Unlock all MCU_CTRL_MMR0 module registers */
  36         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  37         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  38         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  39         mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  40
  41         /* Unlock all CTRL_MMR0 module registers */
  42         mmr_unlock(CTRL_MMR0_BASE, 0);
  43         mmr_unlock(CTRL_MMR0_BASE, 1);
  44         mmr_unlock(CTRL_MMR0_BASE, 2);
  45         mmr_unlock(CTRL_MMR0_BASE, 3);
  46         mmr_unlock(CTRL_MMR0_BASE, 6);
  47         mmr_unlock(CTRL_MMR0_BASE, 7);
  48 }
  49
  50 static void store_boot_index_from_rom(void)
  51 {
  52         u32 *boot_index = (u32 *)K3_BOOT_PARAM_TABLE_INDEX_VAL;
  53
  54         *boot_index = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  55 }
  56
  57 void board_init_f(ulong dummy)
  58 {
  59         /*
  60          * Cannot delay this further as there is a chance that
  61          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  62          */
  63         store_boot_index_from_rom();
  64
  65         /* Make all control module registers accessible */
  66         ctrl_mmr_unlock();
  67
  68         /* Init DM early in-order to invoke system controller */
  69         spl_early_init();
  70
  71         /* Prepare console output */
  72         preloader_console_init();
  73 }
  74
  75 static u32 __get_backup_bootmedia(u32 devstat)
  76 {
  77         u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
  78                         CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
  79
  80         switch (bkup_boot) {
  81         case BACKUP_BOOT_DEVICE_USB:
  82                 return BOOT_DEVICE_USB;
  83         case BACKUP_BOOT_DEVICE_UART:
  84                 return BOOT_DEVICE_UART;
  85         case BACKUP_BOOT_DEVICE_ETHERNET:
  86                 return BOOT_DEVICE_ETHERNET;
  87         case BACKUP_BOOT_DEVICE_MMC2:
  88         {
  89                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
  90                             CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
  91                 if (port == 0x0)
  92                         return BOOT_DEVICE_MMC1;
  93                 return BOOT_DEVICE_MMC2;
  94         }
  95         case BACKUP_BOOT_DEVICE_SPI:
  96                 return BOOT_DEVICE_SPI;
  97         case BACKUP_BOOT_DEVICE_HYPERFLASH:
  98                 return BOOT_DEVICE_HYPERFLASH;
  99         case BACKUP_BOOT_DEVICE_I2C:
 100                 return BOOT_DEVICE_I2C;
 101         };
 102
 103         return BOOT_DEVICE_RAM;
 104 }
 105
 106 static u32 __get_primary_bootmedia(u32 devstat)
 107 {
 108         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 109                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 110
 111         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 112                 bootmode = BOOT_DEVICE_SPI;
 113
 114         if (bootmode == BOOT_DEVICE_MMC2) {
 115                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
 116                             CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
 117                 if (port == 0x0)
 118                         bootmode = BOOT_DEVICE_MMC1;
 119         } else if (bootmode == BOOT_DEVICE_MMC1) {
 120                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
 121                             CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
 122                 if (port == 0x1)
 123                         bootmode = BOOT_DEVICE_MMC2;
 124         }
 125
 126         return bootmode;
 127 }
 128
 129 u32 spl_boot_device(void)
 130 {
 131         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 132         u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL);
 133
 134         if (bootindex == K3_PRIMARY_BOOTMODE)
 135                 return __get_primary_bootmedia(devstat);
 136         else
 137                 return __get_backup_bootmedia(devstat);
 138 }
 139 #endif
 140
 141 #ifndef CONFIG_SYSRESET
 142 void reset_cpu(ulong ignored)
 143 {
 144 }
 145 #endif