arch/arm/mach-k3/am6_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * K3: Architecture initialization
   4  *
   5  * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <spl.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/sysfw-loader.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include "common.h"
  16 #include <dm.h>
  17 #include <dm/uclass-internal.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/soc/ti/ti_sci_protocol.h>
  20
  21 #ifdef CONFIG_SPL_BUILD
  22 static void mmr_unlock(u32 base, u32 partition)
  23 {
  24         /* Translate the base address */
  25         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  26
  27         /* Unlock the requested partition if locked using two-step sequence */
  28         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  29         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  30 }
  31
  32 static void ctrl_mmr_unlock(void)
  33 {
  34         /* Unlock all WKUP_CTRL_MMR0 module registers */
  35         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  36         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  37         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  38         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  39         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  40         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  41
  42         /* Unlock all MCU_CTRL_MMR0 module registers */
  43         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  44         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  45         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  46         mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  47
  48         /* Unlock all CTRL_MMR0 module registers */
  49         mmr_unlock(CTRL_MMR0_BASE, 0);
  50         mmr_unlock(CTRL_MMR0_BASE, 1);
  51         mmr_unlock(CTRL_MMR0_BASE, 2);
  52         mmr_unlock(CTRL_MMR0_BASE, 3);
  53         mmr_unlock(CTRL_MMR0_BASE, 6);
  54         mmr_unlock(CTRL_MMR0_BASE, 7);
  55 }
  56
  57 /*
  58  * This uninitialized global variable would normal end up in the .bss section,
  59  * but the .bss is cleared between writing and reading this variable, so move
  60  * it to the .data section.
  61  */
  62 u32 bootindex __attribute__((section(".data")));
  63
  64 static void store_boot_index_from_rom(void)
  65 {
  66         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  67 }
  68
  69 void board_init_f(ulong dummy)
  70 {
  71 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
  72         struct udevice *dev;
  73         int ret;
  74 #endif
  75         /*
  76          * Cannot delay this further as there is a chance that
  77          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  78          */
  79         store_boot_index_from_rom();
  80
  81         /* Make all control module registers accessible */
  82         ctrl_mmr_unlock();
  83
  84 #ifdef CONFIG_CPU_V7R
  85         setup_k3_mpu_regions();
  86 #endif
  87
  88         /* Init DM early in-order to invoke system controller */
  89         spl_early_init();
  90
  91 #ifdef CONFIG_K3_LOAD_SYSFW
  92         /*
  93          * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
  94          * regardless of the result of pinctrl. Do this without probing the
  95          * device, but instead by searching the device that would request the
  96          * given sequence number if probed. The UART will be used by the system
  97          * firmware (SYSFW) image for various purposes and SYSFW depends on us
  98          * to initialize its pin settings.
  99          */
 100         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
 101         if (!ret)
 102                 pinctrl_select_state(dev, "default");
 103
 104         /*
 105          * Load, start up, and configure system controller firmware. Provide
 106          * the U-Boot console init function to the SYSFW post-PM configuration
 107          * callback hook, effectively switching on (or over) the console
 108          * output.
 109          */
 110         k3_sysfw_loader(preloader_console_init);
 111 #else
 112         /* Prepare console output */
 113         preloader_console_init();
 114 #endif
 115
 116         /* Perform EEPROM-based board detection */
 117         do_board_detect();
 118
 119 #ifdef CONFIG_K3_AM654_DDRSS
 120         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 121         if (ret)
 122                 panic("DRAM init failed: %d\n", ret);
 123 #endif
 124 }
 125
 126 u32 spl_boot_mode(const u32 boot_device)
 127 {
 128 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
 129         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 130
 131         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 132                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 133
 134         /* eMMC boot0 mode is only supported for primary boot */
 135         if (bootindex == K3_PRIMARY_BOOTMODE &&
 136             bootmode == BOOT_DEVICE_MMC1)
 137                 return MMCSD_MODE_EMMCBOOT;
 138 #endif
 139
 140         /* Everything else use filesystem if available */
 141 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 142         return MMCSD_MODE_FS;
 143 #else
 144         return MMCSD_MODE_RAW;
 145 #endif
 146 }
 147
 148 static u32 __get_backup_bootmedia(u32 devstat)
 149 {
 150         u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 151                         CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 152
 153         switch (bkup_boot) {
 154         case BACKUP_BOOT_DEVICE_USB:
 155                 return BOOT_DEVICE_USB;
 156         case BACKUP_BOOT_DEVICE_UART:
 157                 return BOOT_DEVICE_UART;
 158         case BACKUP_BOOT_DEVICE_ETHERNET:
 159                 return BOOT_DEVICE_ETHERNET;
 160         case BACKUP_BOOT_DEVICE_MMC2:
 161         {
 162                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 163                             CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 164                 if (port == 0x0)
 165                         return BOOT_DEVICE_MMC1;
 166                 return BOOT_DEVICE_MMC2;
 167         }
 168         case BACKUP_BOOT_DEVICE_SPI:
 169                 return BOOT_DEVICE_SPI;
 170         case BACKUP_BOOT_DEVICE_HYPERFLASH:
 171                 return BOOT_DEVICE_HYPERFLASH;
 172         case BACKUP_BOOT_DEVICE_I2C:
 173                 return BOOT_DEVICE_I2C;
 174         };
 175
 176         return BOOT_DEVICE_RAM;
 177 }
 178
 179 static u32 __get_primary_bootmedia(u32 devstat)
 180 {
 181         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 182                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 183
 184         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 185                 bootmode = BOOT_DEVICE_SPI;
 186
 187         if (bootmode == BOOT_DEVICE_MMC2) {
 188                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
 189                             CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
 190                 if (port == 0x0)
 191                         bootmode = BOOT_DEVICE_MMC1;
 192         } else if (bootmode == BOOT_DEVICE_MMC1) {
 193                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
 194                             CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
 195                 if (port == 0x1)
 196                         bootmode = BOOT_DEVICE_MMC2;
 197         }
 198
 199         return bootmode;
 200 }
 201
 202 u32 spl_boot_device(void)
 203 {
 204         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 205
 206         if (bootindex == K3_PRIMARY_BOOTMODE)
 207                 return __get_primary_bootmedia(devstat);
 208         else
 209                 return __get_backup_bootmedia(devstat);
 210 }
 211 #endif
 212
 213 #ifdef CONFIG_SYS_K3_SPL_ATF
 214
 215 #define AM6_DEV_MCU_RTI0                        134
 216 #define AM6_DEV_MCU_RTI1                        135
 217 #define AM6_DEV_MCU_ARMSS0_CPU0                 159
 218 #define AM6_DEV_MCU_ARMSS0_CPU1                 245
 219
 220 void release_resources_for_core_shutdown(void)
 221 {
 222         struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 223         struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
 224         struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
 225         int ret;
 226         u32 i;
 227
 228         const u32 put_device_ids[] = {
 229                 AM6_DEV_MCU_RTI0,
 230                 AM6_DEV_MCU_RTI1,
 231         };
 232
 233         /* Iterate through list of devices to put (shutdown) */
 234         for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 235                 u32 id = put_device_ids[i];
 236
 237                 ret = dev_ops->put_device(ti_sci, id);
 238                 if (ret)
 239                         panic("Failed to put device %u (%d)\n", id, ret);
 240         }
 241
 242         const u32 put_core_ids[] = {
 243                 AM6_DEV_MCU_ARMSS0_CPU1,
 244                 AM6_DEV_MCU_ARMSS0_CPU0,        /* Handle CPU0 after CPU1 */
 245         };
 246
 247         /* Iterate through list of cores to put (shutdown) */
 248         for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
 249                 u32 id = put_core_ids[i];
 250
 251                 /*
 252                  * Queue up the core shutdown request. Note that this call
 253                  * needs to be followed up by an actual invocation of an WFE
 254                  * or WFI CPU instruction.
 255                  */
 256                 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
 257                 if (ret)
 258                         panic("Failed sending core %u shutdown message (%d)\n",
 259                               id, ret);
 260         }
 261 }
 262 #endif