arch/arm/mach-k3/am6_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AM6: SoC specific initialization
   4  *
   5  * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <spl.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/sysfw-loader.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include "common.h"
  16 #include <dm.h>
  17 #include <dm/uclass-internal.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/soc/ti/ti_sci_protocol.h>
  20
  21 #ifdef CONFIG_SPL_BUILD
  22 static void mmr_unlock(u32 base, u32 partition)
  23 {
  24         /* Translate the base address */
  25         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  26
  27         /* Unlock the requested partition if locked using two-step sequence */
  28         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  29         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  30 }
  31
  32 static void ctrl_mmr_unlock(void)
  33 {
  34         /* Unlock all WKUP_CTRL_MMR0 module registers */
  35         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  36         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  37         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  38         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  39         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  40         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  41
  42         /* Unlock all MCU_CTRL_MMR0 module registers */
  43         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  44         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  45         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  46         mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  47
  48         /* Unlock all CTRL_MMR0 module registers */
  49         mmr_unlock(CTRL_MMR0_BASE, 0);
  50         mmr_unlock(CTRL_MMR0_BASE, 1);
  51         mmr_unlock(CTRL_MMR0_BASE, 2);
  52         mmr_unlock(CTRL_MMR0_BASE, 3);
  53         mmr_unlock(CTRL_MMR0_BASE, 6);
  54         mmr_unlock(CTRL_MMR0_BASE, 7);
  55 }
  56
  57 /*
  58  * This uninitialized global variable would normal end up in the .bss section,
  59  * but the .bss is cleared between writing and reading this variable, so move
  60  * it to the .data section.
  61  */
  62 u32 bootindex __attribute__((section(".data")));
  63
  64 static void store_boot_index_from_rom(void)
  65 {
  66         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  67 }
  68
  69 void board_init_f(ulong dummy)
  70 {
  71 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
  72         struct udevice *dev;
  73         int ret;
  74 #endif
  75         /*
  76          * Cannot delay this further as there is a chance that
  77          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  78          */
  79         store_boot_index_from_rom();
  80
  81         /* Make all control module registers accessible */
  82         ctrl_mmr_unlock();
  83
  84 #ifdef CONFIG_CPU_V7R
  85         disable_linefill_optimization();
  86         setup_k3_mpu_regions();
  87 #endif
  88
  89         /* Init DM early in-order to invoke system controller */
  90         spl_early_init();
  91
  92 #ifdef CONFIG_K3_LOAD_SYSFW
  93         /*
  94          * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
  95          * regardless of the result of pinctrl. Do this without probing the
  96          * device, but instead by searching the device that would request the
  97          * given sequence number if probed. The UART will be used by the system
  98          * firmware (SYSFW) image for various purposes and SYSFW depends on us
  99          * to initialize its pin settings.
 100          */
 101         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
 102         if (!ret)
 103                 pinctrl_select_state(dev, "default");
 104
 105         /*
 106          * Load, start up, and configure system controller firmware. Provide
 107          * the U-Boot console init function to the SYSFW post-PM configuration
 108          * callback hook, effectively switching on (or over) the console
 109          * output.
 110          */
 111         k3_sysfw_loader(preloader_console_init);
 112 #else
 113         /* Prepare console output */
 114         preloader_console_init();
 115 #endif
 116
 117         /* Perform EEPROM-based board detection */
 118         do_board_detect();
 119
 120 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 121         ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
 122                                           &dev);
 123         if (ret)
 124                 printf("AVS init failed: %d\n", ret);
 125 #endif
 126
 127 #ifdef CONFIG_K3_AM654_DDRSS
 128         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 129         if (ret)
 130                 panic("DRAM init failed: %d\n", ret);
 131 #endif
 132 }
 133
 134 u32 spl_boot_mode(const u32 boot_device)
 135 {
 136 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
 137         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 138
 139         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 140                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 141
 142         /* eMMC boot0 mode is only supported for primary boot */
 143         if (bootindex == K3_PRIMARY_BOOTMODE &&
 144             bootmode == BOOT_DEVICE_MMC1)
 145                 return MMCSD_MODE_EMMCBOOT;
 146 #endif
 147
 148         /* Everything else use filesystem if available */
 149 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 150         return MMCSD_MODE_FS;
 151 #else
 152         return MMCSD_MODE_RAW;
 153 #endif
 154 }
 155
 156 static u32 __get_backup_bootmedia(u32 devstat)
 157 {
 158         u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 159                         CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 160
 161         switch (bkup_boot) {
 162         case BACKUP_BOOT_DEVICE_USB:
 163                 return BOOT_DEVICE_USB;
 164         case BACKUP_BOOT_DEVICE_UART:
 165                 return BOOT_DEVICE_UART;
 166         case BACKUP_BOOT_DEVICE_ETHERNET:
 167                 return BOOT_DEVICE_ETHERNET;
 168         case BACKUP_BOOT_DEVICE_MMC2:
 169         {
 170                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 171                             CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 172                 if (port == 0x0)
 173                         return BOOT_DEVICE_MMC1;
 174                 return BOOT_DEVICE_MMC2;
 175         }
 176         case BACKUP_BOOT_DEVICE_SPI:
 177                 return BOOT_DEVICE_SPI;
 178         case BACKUP_BOOT_DEVICE_HYPERFLASH:
 179                 return BOOT_DEVICE_HYPERFLASH;
 180         case BACKUP_BOOT_DEVICE_I2C:
 181                 return BOOT_DEVICE_I2C;
 182         };
 183
 184         return BOOT_DEVICE_RAM;
 185 }
 186
 187 static u32 __get_primary_bootmedia(u32 devstat)
 188 {
 189         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 190                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 191
 192         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 193                 bootmode = BOOT_DEVICE_SPI;
 194
 195         if (bootmode == BOOT_DEVICE_MMC2) {
 196                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
 197                             CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
 198                 if (port == 0x0)
 199                         bootmode = BOOT_DEVICE_MMC1;
 200         } else if (bootmode == BOOT_DEVICE_MMC1) {
 201                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
 202                             CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
 203                 if (port == 0x1)
 204                         bootmode = BOOT_DEVICE_MMC2;
 205         }
 206
 207         return bootmode;
 208 }
 209
 210 u32 spl_boot_device(void)
 211 {
 212         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 213
 214         if (bootindex == K3_PRIMARY_BOOTMODE)
 215                 return __get_primary_bootmedia(devstat);
 216         else
 217                 return __get_backup_bootmedia(devstat);
 218 }
 219 #endif
 220
 221 #ifdef CONFIG_SYS_K3_SPL_ATF
 222
 223 #define AM6_DEV_MCU_RTI0                        134
 224 #define AM6_DEV_MCU_RTI1                        135
 225 #define AM6_DEV_MCU_ARMSS0_CPU0                 159
 226 #define AM6_DEV_MCU_ARMSS0_CPU1                 245
 227
 228 void release_resources_for_core_shutdown(void)
 229 {
 230         struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 231         struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
 232         struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
 233         int ret;
 234         u32 i;
 235
 236         const u32 put_device_ids[] = {
 237                 AM6_DEV_MCU_RTI0,
 238                 AM6_DEV_MCU_RTI1,
 239         };
 240
 241         /* Iterate through list of devices to put (shutdown) */
 242         for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 243                 u32 id = put_device_ids[i];
 244
 245                 ret = dev_ops->put_device(ti_sci, id);
 246                 if (ret)
 247                         panic("Failed to put device %u (%d)\n", id, ret);
 248         }
 249
 250         const u32 put_core_ids[] = {
 251                 AM6_DEV_MCU_ARMSS0_CPU1,
 252                 AM6_DEV_MCU_ARMSS0_CPU0,        /* Handle CPU0 after CPU1 */
 253         };
 254
 255         /* Iterate through list of cores to put (shutdown) */
 256         for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
 257                 u32 id = put_core_ids[i];
 258
 259                 /*
 260                  * Queue up the core shutdown request. Note that this call
 261                  * needs to be followed up by an actual invocation of an WFE
 262                  * or WFI CPU instruction.
 263                  */
 264                 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
 265                 if (ret)
 266                         panic("Failed sending core %u shutdown message (%d)\n",
 267                               id, ret);
 268         }
 269 }
 270 #endif