arch/arm/mach-k3/am6_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AM6: SoC specific initialization
   4  *
   5  * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <spl.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/sysfw-loader.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include "common.h"
  16 #include <dm.h>
  17 #include <dm/uclass-internal.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/soc/ti/ti_sci_protocol.h>
  20
  21 #ifdef CONFIG_SPL_BUILD
  22 #ifdef CONFIG_K3_LOAD_SYSFW
  23 #ifdef CONFIG_TI_SECURE_DEVICE
  24 struct fwl_data main_cbass_fwls[] = {
  25         { "MMCSD1_CFG", 2057, 1 },
  26         { "MMCSD0_CFG", 2058, 1 },
  27         { "USB3SS0_SLV0", 2176, 2 },
  28         { "PCIE0_SLV", 2336, 8 },
  29         { "PCIE1_SLV", 2337, 8 },
  30         { "PCIE0_CFG", 2688, 1 },
  31         { "PCIE1_CFG", 2689, 1 },
  32 }, mcu_cbass_fwls[] = {
  33         { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
  34         { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
  35         { "MCU_FSS0_S1", 1033, 8 },
  36         { "MCU_FSS0_S0", 1036, 8 },
  37         { "MCU_CPSW0", 1220, 1 },
  38 };
  39 #endif
  40 #endif
  41
  42 static void mmr_unlock(u32 base, u32 partition)
  43 {
  44         /* Translate the base address */
  45         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  46
  47         /* Unlock the requested partition if locked using two-step sequence */
  48         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  49         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  50 }
  51
  52 static void ctrl_mmr_unlock(void)
  53 {
  54         /* Unlock all WKUP_CTRL_MMR0 module registers */
  55         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  56         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  57         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  58         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  59         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  60         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  61
  62         /* Unlock all MCU_CTRL_MMR0 module registers */
  63         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  64         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  65         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  66         mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  67
  68         /* Unlock all CTRL_MMR0 module registers */
  69         mmr_unlock(CTRL_MMR0_BASE, 0);
  70         mmr_unlock(CTRL_MMR0_BASE, 1);
  71         mmr_unlock(CTRL_MMR0_BASE, 2);
  72         mmr_unlock(CTRL_MMR0_BASE, 3);
  73         mmr_unlock(CTRL_MMR0_BASE, 6);
  74         mmr_unlock(CTRL_MMR0_BASE, 7);
  75 }
  76
  77 /*
  78  * This uninitialized global variable would normal end up in the .bss section,
  79  * but the .bss is cleared between writing and reading this variable, so move
  80  * it to the .data section.
  81  */
  82 u32 bootindex __attribute__((section(".data")));
  83
  84 static void store_boot_index_from_rom(void)
  85 {
  86         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  87 }
  88
  89 void board_init_f(ulong dummy)
  90 {
  91 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
  92         struct udevice *dev;
  93         int ret;
  94 #endif
  95         /*
  96          * Cannot delay this further as there is a chance that
  97          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  98          */
  99         store_boot_index_from_rom();
 100
 101         /* Make all control module registers accessible */
 102         ctrl_mmr_unlock();
 103
 104 #ifdef CONFIG_CPU_V7R
 105         disable_linefill_optimization();
 106         setup_k3_mpu_regions();
 107 #endif
 108
 109         /* Init DM early in-order to invoke system controller */
 110         spl_early_init();
 111
 112 #ifdef CONFIG_K3_EARLY_CONS
 113         /*
 114          * Allow establishing an early console as required for example when
 115          * doing a UART-based boot. Note that this console may not "survive"
 116          * through a SYSFW PM-init step and will need a re-init in some way
 117          * due to changing module clock frequencies.
 118          */
 119         early_console_init();
 120 #endif
 121
 122 #ifdef CONFIG_K3_LOAD_SYSFW
 123         /*
 124          * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
 125          * regardless of the result of pinctrl. Do this without probing the
 126          * device, but instead by searching the device that would request the
 127          * given sequence number if probed. The UART will be used by the system
 128          * firmware (SYSFW) image for various purposes and SYSFW depends on us
 129          * to initialize its pin settings.
 130          */
 131         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
 132         if (!ret)
 133                 pinctrl_select_state(dev, "default");
 134
 135         /*
 136          * Load, start up, and configure system controller firmware while
 137          * also populating the SYSFW post-PM configuration callback hook.
 138          */
 139         k3_sysfw_loader(preloader_console_init);
 140
 141         /* Disable ROM configured firewalls right after loading sysfw */
 142 #ifdef CONFIG_TI_SECURE_DEVICE
 143         remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
 144         remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
 145 #endif
 146 #else
 147         /* Prepare console output */
 148         preloader_console_init();
 149 #endif
 150
 151         /* Output System Firmware version info */
 152         k3_sysfw_print_ver();
 153
 154         /* Perform EEPROM-based board detection */
 155         do_board_detect();
 156
 157 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 158         ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
 159                                           &dev);
 160         if (ret)
 161                 printf("AVS init failed: %d\n", ret);
 162 #endif
 163
 164 #ifdef CONFIG_K3_AM654_DDRSS
 165         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 166         if (ret)
 167                 panic("DRAM init failed: %d\n", ret);
 168 #endif
 169 }
 170
 171 u32 spl_boot_mode(const u32 boot_device)
 172 {
 173 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
 174         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 175
 176         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 177                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 178
 179         /* eMMC boot0 mode is only supported for primary boot */
 180         if (bootindex == K3_PRIMARY_BOOTMODE &&
 181             bootmode == BOOT_DEVICE_MMC1)
 182                 return MMCSD_MODE_EMMCBOOT;
 183 #endif
 184
 185         /* Everything else use filesystem if available */
 186 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 187         return MMCSD_MODE_FS;
 188 #else
 189         return MMCSD_MODE_RAW;
 190 #endif
 191 }
 192
 193 static u32 __get_backup_bootmedia(u32 devstat)
 194 {
 195         u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 196                         CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 197
 198         switch (bkup_boot) {
 199         case BACKUP_BOOT_DEVICE_USB:
 200                 return BOOT_DEVICE_USB;
 201         case BACKUP_BOOT_DEVICE_UART:
 202                 return BOOT_DEVICE_UART;
 203         case BACKUP_BOOT_DEVICE_ETHERNET:
 204                 return BOOT_DEVICE_ETHERNET;
 205         case BACKUP_BOOT_DEVICE_MMC2:
 206         {
 207                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 208                             CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 209                 if (port == 0x0)
 210                         return BOOT_DEVICE_MMC1;
 211                 return BOOT_DEVICE_MMC2;
 212         }
 213         case BACKUP_BOOT_DEVICE_SPI:
 214                 return BOOT_DEVICE_SPI;
 215         case BACKUP_BOOT_DEVICE_HYPERFLASH:
 216                 return BOOT_DEVICE_HYPERFLASH;
 217         case BACKUP_BOOT_DEVICE_I2C:
 218                 return BOOT_DEVICE_I2C;
 219         };
 220
 221         return BOOT_DEVICE_RAM;
 222 }
 223
 224 static u32 __get_primary_bootmedia(u32 devstat)
 225 {
 226         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 227                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 228
 229         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 230                 bootmode = BOOT_DEVICE_SPI;
 231
 232         if (bootmode == BOOT_DEVICE_MMC2) {
 233                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
 234                             CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
 235                 if (port == 0x0)
 236                         bootmode = BOOT_DEVICE_MMC1;
 237         } else if (bootmode == BOOT_DEVICE_MMC1) {
 238                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
 239                             CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
 240                 if (port == 0x1)
 241                         bootmode = BOOT_DEVICE_MMC2;
 242         }
 243
 244         return bootmode;
 245 }
 246
 247 u32 spl_boot_device(void)
 248 {
 249         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 250
 251         if (bootindex == K3_PRIMARY_BOOTMODE)
 252                 return __get_primary_bootmedia(devstat);
 253         else
 254                 return __get_backup_bootmedia(devstat);
 255 }
 256 #endif
 257
 258 #ifdef CONFIG_SYS_K3_SPL_ATF
 259
 260 #define AM6_DEV_MCU_RTI0                        134
 261 #define AM6_DEV_MCU_RTI1                        135
 262 #define AM6_DEV_MCU_ARMSS0_CPU0                 159
 263 #define AM6_DEV_MCU_ARMSS0_CPU1                 245
 264
 265 void release_resources_for_core_shutdown(void)
 266 {
 267         struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 268         struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
 269         struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
 270         int ret;
 271         u32 i;
 272
 273         const u32 put_device_ids[] = {
 274                 AM6_DEV_MCU_RTI0,
 275                 AM6_DEV_MCU_RTI1,
 276         };
 277
 278         /* Iterate through list of devices to put (shutdown) */
 279         for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 280                 u32 id = put_device_ids[i];
 281
 282                 ret = dev_ops->put_device(ti_sci, id);
 283                 if (ret)
 284                         panic("Failed to put device %u (%d)\n", id, ret);
 285         }
 286
 287         const u32 put_core_ids[] = {
 288                 AM6_DEV_MCU_ARMSS0_CPU1,
 289                 AM6_DEV_MCU_ARMSS0_CPU0,        /* Handle CPU0 after CPU1 */
 290         };
 291
 292         /* Iterate through list of cores to put (shutdown) */
 293         for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
 294                 u32 id = put_core_ids[i];
 295
 296                 /*
 297                  * Queue up the core shutdown request. Note that this call
 298                  * needs to be followed up by an actual invocation of an WFE
 299                  * or WFI CPU instruction.
 300                  */
 301                 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
 302                 if (ret)
 303                         panic("Failed sending core %u shutdown message (%d)\n",
 304                               id, ret);
 305         }
 306 }
 307 #endif