arch/arm/mach-k3/am6_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * K3: Architecture initialization
   4  *
   5  * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <spl.h>
  12 #include <asm/arch/hardware.h>
  13 #include "common.h"
  14 #include <dm.h>
  15
  16 #ifdef CONFIG_SPL_BUILD
  17 static void mmr_unlock(u32 base, u32 partition)
  18 {
  19         /* Translate the base address */
  20         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  21
  22         /* Unlock the requested partition if locked using two-step sequence */
  23         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  24         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  25 }
  26
  27 static void ctrl_mmr_unlock(void)
  28 {
  29         /* Unlock all WKUP_CTRL_MMR0 module registers */
  30         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  31         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  32         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  33         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  34         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  35         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  36
  37         /* Unlock all MCU_CTRL_MMR0 module registers */
  38         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  39         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  40         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  41         mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  42
  43         /* Unlock all CTRL_MMR0 module registers */
  44         mmr_unlock(CTRL_MMR0_BASE, 0);
  45         mmr_unlock(CTRL_MMR0_BASE, 1);
  46         mmr_unlock(CTRL_MMR0_BASE, 2);
  47         mmr_unlock(CTRL_MMR0_BASE, 3);
  48         mmr_unlock(CTRL_MMR0_BASE, 6);
  49         mmr_unlock(CTRL_MMR0_BASE, 7);
  50 }
  51
  52 /*
  53  * This uninitialized global variable would normal end up in the .bss section,
  54  * but the .bss is cleared between writing and reading this variable, so move
  55  * it to the .data section.
  56  */
  57 u32 bootindex __attribute__((section(".data")));
  58
  59 static void store_boot_index_from_rom(void)
  60 {
  61         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  62 }
  63
  64 void board_init_f(ulong dummy)
  65 {
  66 #if defined(CONFIG_K3_AM654_DDRSS)
  67         struct udevice *dev;
  68         int ret;
  69 #endif
  70         /*
  71          * Cannot delay this further as there is a chance that
  72          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  73          */
  74         store_boot_index_from_rom();
  75
  76         /* Make all control module registers accessible */
  77         ctrl_mmr_unlock();
  78
  79 #ifdef CONFIG_CPU_V7R
  80         setup_k3_mpu_regions();
  81 #endif
  82
  83         /* Init DM early in-order to invoke system controller */
  84         spl_early_init();
  85
  86         /* Prepare console output */
  87         preloader_console_init();
  88
  89 #ifdef CONFIG_K3_AM654_DDRSS
  90         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  91         if (ret)
  92                 panic("DRAM init failed: %d\n", ret);
  93 #endif
  94 }
  95
  96 u32 spl_boot_mode(const u32 boot_device)
  97 {
  98 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
  99         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 100
 101         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 102                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 103
 104         /* eMMC boot0 mode is only supported for primary boot */
 105         if (bootindex == K3_PRIMARY_BOOTMODE &&
 106             bootmode == BOOT_DEVICE_MMC1)
 107                 return MMCSD_MODE_EMMCBOOT;
 108 #endif
 109
 110         /* Everything else use filesystem if available */
 111 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 112         return MMCSD_MODE_FS;
 113 #else
 114         return MMCSD_MODE_RAW;
 115 #endif
 116 }
 117
 118 static u32 __get_backup_bootmedia(u32 devstat)
 119 {
 120         u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 121                         CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 122
 123         switch (bkup_boot) {
 124         case BACKUP_BOOT_DEVICE_USB:
 125                 return BOOT_DEVICE_USB;
 126         case BACKUP_BOOT_DEVICE_UART:
 127                 return BOOT_DEVICE_UART;
 128         case BACKUP_BOOT_DEVICE_ETHERNET:
 129                 return BOOT_DEVICE_ETHERNET;
 130         case BACKUP_BOOT_DEVICE_MMC2:
 131         {
 132                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 133                             CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 134                 if (port == 0x0)
 135                         return BOOT_DEVICE_MMC1;
 136                 return BOOT_DEVICE_MMC2;
 137         }
 138         case BACKUP_BOOT_DEVICE_SPI:
 139                 return BOOT_DEVICE_SPI;
 140         case BACKUP_BOOT_DEVICE_HYPERFLASH:
 141                 return BOOT_DEVICE_HYPERFLASH;
 142         case BACKUP_BOOT_DEVICE_I2C:
 143                 return BOOT_DEVICE_I2C;
 144         };
 145
 146         return BOOT_DEVICE_RAM;
 147 }
 148
 149 static u32 __get_primary_bootmedia(u32 devstat)
 150 {
 151         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 152                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 153
 154         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 155                 bootmode = BOOT_DEVICE_SPI;
 156
 157         if (bootmode == BOOT_DEVICE_MMC2) {
 158                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
 159                             CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
 160                 if (port == 0x0)
 161                         bootmode = BOOT_DEVICE_MMC1;
 162         } else if (bootmode == BOOT_DEVICE_MMC1) {
 163                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
 164                             CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
 165                 if (port == 0x1)
 166                         bootmode = BOOT_DEVICE_MMC2;
 167         }
 168
 169         return bootmode;
 170 }
 171
 172 u32 spl_boot_device(void)
 173 {
 174         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 175
 176         if (bootindex == K3_PRIMARY_BOOTMODE)
 177                 return __get_primary_bootmedia(devstat);
 178         else
 179                 return __get_backup_bootmedia(devstat);
 180 }
 181 #endif
 182
 183 #ifndef CONFIG_SYSRESET
 184 void reset_cpu(ulong ignored)
 185 {
 186 }
 187 #endif