arch/arm/mach-k3/am6_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AM6: SoC specific initialization
   4  *
   5  * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <spl.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/sysfw-loader.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include "common.h"
  16 #include <dm.h>
  17 #include <dm/uclass-internal.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/soc/ti/ti_sci_protocol.h>
  20 #include <mmc.h>
  21
  22 #ifdef CONFIG_SPL_BUILD
  23 #ifdef CONFIG_K3_LOAD_SYSFW
  24 #ifdef CONFIG_TI_SECURE_DEVICE
  25 struct fwl_data main_cbass_fwls[] = {
  26         { "MMCSD1_CFG", 2057, 1 },
  27         { "MMCSD0_CFG", 2058, 1 },
  28         { "USB3SS0_SLV0", 2176, 2 },
  29         { "PCIE0_SLV", 2336, 8 },
  30         { "PCIE1_SLV", 2337, 8 },
  31         { "PCIE0_CFG", 2688, 1 },
  32         { "PCIE1_CFG", 2689, 1 },
  33 }, mcu_cbass_fwls[] = {
  34         { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
  35         { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
  36         { "MCU_FSS0_S1", 1033, 8 },
  37         { "MCU_FSS0_S0", 1036, 8 },
  38         { "MCU_CPSW0", 1220, 1 },
  39 };
  40 #endif
  41 #endif
  42
  43 static void mmr_unlock(u32 base, u32 partition)
  44 {
  45         /* Translate the base address */
  46         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  47
  48         /* Unlock the requested partition if locked using two-step sequence */
  49         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  50         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  51 }
  52
  53 static void ctrl_mmr_unlock(void)
  54 {
  55         /* Unlock all WKUP_CTRL_MMR0 module registers */
  56         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  57         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  58         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  59         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  60         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  61         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  62
  63         /* Unlock all MCU_CTRL_MMR0 module registers */
  64         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  65         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  66         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  67         mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  68
  69         /* Unlock all CTRL_MMR0 module registers */
  70         mmr_unlock(CTRL_MMR0_BASE, 0);
  71         mmr_unlock(CTRL_MMR0_BASE, 1);
  72         mmr_unlock(CTRL_MMR0_BASE, 2);
  73         mmr_unlock(CTRL_MMR0_BASE, 3);
  74         mmr_unlock(CTRL_MMR0_BASE, 6);
  75         mmr_unlock(CTRL_MMR0_BASE, 7);
  76 }
  77
  78 /*
  79  * This uninitialized global variable would normal end up in the .bss section,
  80  * but the .bss is cleared between writing and reading this variable, so move
  81  * it to the .data section.
  82  */
  83 u32 bootindex __attribute__((section(".data")));
  84
  85 static void store_boot_index_from_rom(void)
  86 {
  87         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  88 }
  89
  90 #if defined(CONFIG_K3_LOAD_SYSFW)
  91 void k3_mmc_stop_clock(void)
  92 {
  93         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  94                 struct mmc *mmc = find_mmc_device(0);
  95
  96                 if (!mmc)
  97                         return;
  98
  99                 mmc->saved_clock = mmc->clock;
 100                 mmc_set_clock(mmc, 0, true);
 101         }
 102 }
 103
 104 void k3_mmc_restart_clock(void)
 105 {
 106         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 107                 struct mmc *mmc = find_mmc_device(0);
 108
 109                 if (!mmc)
 110                         return;
 111
 112                 mmc_set_clock(mmc, mmc->saved_clock, false);
 113         }
 114 }
 115 #endif
 116
 117 void board_init_f(ulong dummy)
 118 {
 119 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
 120         struct udevice *dev;
 121         int ret;
 122 #endif
 123         /*
 124          * Cannot delay this further as there is a chance that
 125          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
 126          */
 127         store_boot_index_from_rom();
 128
 129         /* Make all control module registers accessible */
 130         ctrl_mmr_unlock();
 131
 132 #ifdef CONFIG_CPU_V7R
 133         disable_linefill_optimization();
 134         setup_k3_mpu_regions();
 135 #endif
 136
 137         /* Init DM early in-order to invoke system controller */
 138         spl_early_init();
 139
 140 #ifdef CONFIG_K3_EARLY_CONS
 141         /*
 142          * Allow establishing an early console as required for example when
 143          * doing a UART-based boot. Note that this console may not "survive"
 144          * through a SYSFW PM-init step and will need a re-init in some way
 145          * due to changing module clock frequencies.
 146          */
 147         early_console_init();
 148 #endif
 149
 150 #ifdef CONFIG_K3_LOAD_SYSFW
 151         /*
 152          * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
 153          * regardless of the result of pinctrl. Do this without probing the
 154          * device, but instead by searching the device that would request the
 155          * given sequence number if probed. The UART will be used by the system
 156          * firmware (SYSFW) image for various purposes and SYSFW depends on us
 157          * to initialize its pin settings.
 158          */
 159         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
 160         if (!ret)
 161                 pinctrl_select_state(dev, "default");
 162
 163         /*
 164          * Load, start up, and configure system controller firmware while
 165          * also populating the SYSFW post-PM configuration callback hook.
 166          */
 167         k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
 168
 169         /* Prepare console output */
 170         preloader_console_init();
 171
 172         /* Disable ROM configured firewalls right after loading sysfw */
 173 #ifdef CONFIG_TI_SECURE_DEVICE
 174         remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
 175         remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
 176 #endif
 177 #else
 178         /* Prepare console output */
 179         preloader_console_init();
 180 #endif
 181
 182         /* Output System Firmware version info */
 183         k3_sysfw_print_ver();
 184
 185         /* Perform EEPROM-based board detection */
 186         do_board_detect();
 187
 188 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 189         ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
 190                                           &dev);
 191         if (ret)
 192                 printf("AVS init failed: %d\n", ret);
 193 #endif
 194
 195 #ifdef CONFIG_K3_AM654_DDRSS
 196         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 197         if (ret)
 198                 panic("DRAM init failed: %d\n", ret);
 199 #endif
 200 }
 201
 202 u32 spl_boot_mode(const u32 boot_device)
 203 {
 204 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
 205         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 206
 207         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 208                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 209
 210         /* eMMC boot0 mode is only supported for primary boot */
 211         if (bootindex == K3_PRIMARY_BOOTMODE &&
 212             bootmode == BOOT_DEVICE_MMC1)
 213                 return MMCSD_MODE_EMMCBOOT;
 214 #endif
 215
 216         /* Everything else use filesystem if available */
 217 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 218         return MMCSD_MODE_FS;
 219 #else
 220         return MMCSD_MODE_RAW;
 221 #endif
 222 }
 223
 224 static u32 __get_backup_bootmedia(u32 devstat)
 225 {
 226         u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 227                         CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 228
 229         switch (bkup_boot) {
 230         case BACKUP_BOOT_DEVICE_USB:
 231                 return BOOT_DEVICE_USB;
 232         case BACKUP_BOOT_DEVICE_UART:
 233                 return BOOT_DEVICE_UART;
 234         case BACKUP_BOOT_DEVICE_ETHERNET:
 235                 return BOOT_DEVICE_ETHERNET;
 236         case BACKUP_BOOT_DEVICE_MMC2:
 237         {
 238                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 239                             CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 240                 if (port == 0x0)
 241                         return BOOT_DEVICE_MMC1;
 242                 return BOOT_DEVICE_MMC2;
 243         }
 244         case BACKUP_BOOT_DEVICE_SPI:
 245                 return BOOT_DEVICE_SPI;
 246         case BACKUP_BOOT_DEVICE_HYPERFLASH:
 247                 return BOOT_DEVICE_HYPERFLASH;
 248         case BACKUP_BOOT_DEVICE_I2C:
 249                 return BOOT_DEVICE_I2C;
 250         };
 251
 252         return BOOT_DEVICE_RAM;
 253 }
 254
 255 static u32 __get_primary_bootmedia(u32 devstat)
 256 {
 257         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 258                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 259
 260         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 261                 bootmode = BOOT_DEVICE_SPI;
 262
 263         if (bootmode == BOOT_DEVICE_MMC2) {
 264                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
 265                             CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
 266                 if (port == 0x0)
 267                         bootmode = BOOT_DEVICE_MMC1;
 268         } else if (bootmode == BOOT_DEVICE_MMC1) {
 269                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
 270                             CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
 271                 if (port == 0x1)
 272                         bootmode = BOOT_DEVICE_MMC2;
 273         }
 274
 275         return bootmode;
 276 }
 277
 278 u32 spl_boot_device(void)
 279 {
 280         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 281
 282         if (bootindex == K3_PRIMARY_BOOTMODE)
 283                 return __get_primary_bootmedia(devstat);
 284         else
 285                 return __get_backup_bootmedia(devstat);
 286 }
 287 #endif
 288
 289 #ifdef CONFIG_SYS_K3_SPL_ATF
 290
 291 #define AM6_DEV_MCU_RTI0                        134
 292 #define AM6_DEV_MCU_RTI1                        135
 293 #define AM6_DEV_MCU_ARMSS0_CPU0                 159
 294 #define AM6_DEV_MCU_ARMSS0_CPU1                 245
 295
 296 void release_resources_for_core_shutdown(void)
 297 {
 298         struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 299         struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
 300         struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
 301         int ret;
 302         u32 i;
 303
 304         const u32 put_device_ids[] = {
 305                 AM6_DEV_MCU_RTI0,
 306                 AM6_DEV_MCU_RTI1,
 307         };
 308
 309         /* Iterate through list of devices to put (shutdown) */
 310         for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 311                 u32 id = put_device_ids[i];
 312
 313                 ret = dev_ops->put_device(ti_sci, id);
 314                 if (ret)
 315                         panic("Failed to put device %u (%d)\n", id, ret);
 316         }
 317
 318         const u32 put_core_ids[] = {
 319                 AM6_DEV_MCU_ARMSS0_CPU1,
 320                 AM6_DEV_MCU_ARMSS0_CPU0,        /* Handle CPU0 after CPU1 */
 321         };
 322
 323         /* Iterate through list of cores to put (shutdown) */
 324         for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
 325                 u32 id = put_core_ids[i];
 326
 327                 /*
 328                  * Queue up the core shutdown request. Note that this call
 329                  * needs to be followed up by an actual invocation of an WFE
 330                  * or WFI CPU instruction.
 331                  */
 332                 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
 333                 if (ret)
 334                         panic("Failed sending core %u shutdown message (%d)\n",
 335                               id, ret);
 336         }
 337 }
 338 #endif