armv7R: K3: am654: Enable MPU regions
[oweals/u-boot.git] / arch / arm / mach-k3 / am6_init.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * K3: Architecture initialization
4  *
5  * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6  *      Lokesh Vutla <lokeshvutla@ti.com>
7  */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <spl.h>
12 #include <asm/arch/hardware.h>
13 #include "common.h"
14
15 #ifdef CONFIG_SPL_BUILD
16 static void mmr_unlock(u32 base, u32 partition)
17 {
18         /* Translate the base address */
19         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
20
21         /* Unlock the requested partition if locked using two-step sequence */
22         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
23         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
24 }
25
26 static void ctrl_mmr_unlock(void)
27 {
28         /* Unlock all WKUP_CTRL_MMR0 module registers */
29         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
30         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
31         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
32         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
33         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
34         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
35
36         /* Unlock all MCU_CTRL_MMR0 module registers */
37         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
38         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
39         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
40         mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
41
42         /* Unlock all CTRL_MMR0 module registers */
43         mmr_unlock(CTRL_MMR0_BASE, 0);
44         mmr_unlock(CTRL_MMR0_BASE, 1);
45         mmr_unlock(CTRL_MMR0_BASE, 2);
46         mmr_unlock(CTRL_MMR0_BASE, 3);
47         mmr_unlock(CTRL_MMR0_BASE, 6);
48         mmr_unlock(CTRL_MMR0_BASE, 7);
49 }
50
51 static void store_boot_index_from_rom(void)
52 {
53         u32 *boot_index = (u32 *)K3_BOOT_PARAM_TABLE_INDEX_VAL;
54
55         *boot_index = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
56 }
57
58 void board_init_f(ulong dummy)
59 {
60         /*
61          * Cannot delay this further as there is a chance that
62          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
63          */
64         store_boot_index_from_rom();
65
66         /* Make all control module registers accessible */
67         ctrl_mmr_unlock();
68
69 #ifdef CONFIG_CPU_V7R
70         setup_k3_mpu_regions();
71 #endif
72
73         /* Init DM early in-order to invoke system controller */
74         spl_early_init();
75
76         /* Prepare console output */
77         preloader_console_init();
78 }
79
80 u32 spl_boot_mode(const u32 boot_device)
81 {
82 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
83         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
84         u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL);
85
86         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
87                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
88
89         /* eMMC boot0 mode is only supported for primary boot */
90         if (bootindex == K3_PRIMARY_BOOTMODE &&
91             bootmode == BOOT_DEVICE_MMC1)
92                 return MMCSD_MODE_EMMCBOOT;
93 #endif
94
95         /* Everything else use filesystem if available */
96 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
97         return MMCSD_MODE_FS;
98 #else
99         return MMCSD_MODE_RAW;
100 #endif
101 }
102
103 static u32 __get_backup_bootmedia(u32 devstat)
104 {
105         u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
106                         CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
107
108         switch (bkup_boot) {
109         case BACKUP_BOOT_DEVICE_USB:
110                 return BOOT_DEVICE_USB;
111         case BACKUP_BOOT_DEVICE_UART:
112                 return BOOT_DEVICE_UART;
113         case BACKUP_BOOT_DEVICE_ETHERNET:
114                 return BOOT_DEVICE_ETHERNET;
115         case BACKUP_BOOT_DEVICE_MMC2:
116         {
117                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
118                             CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
119                 if (port == 0x0)
120                         return BOOT_DEVICE_MMC1;
121                 return BOOT_DEVICE_MMC2;
122         }
123         case BACKUP_BOOT_DEVICE_SPI:
124                 return BOOT_DEVICE_SPI;
125         case BACKUP_BOOT_DEVICE_HYPERFLASH:
126                 return BOOT_DEVICE_HYPERFLASH;
127         case BACKUP_BOOT_DEVICE_I2C:
128                 return BOOT_DEVICE_I2C;
129         };
130
131         return BOOT_DEVICE_RAM;
132 }
133
134 static u32 __get_primary_bootmedia(u32 devstat)
135 {
136         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
137                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
138
139         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
140                 bootmode = BOOT_DEVICE_SPI;
141
142         if (bootmode == BOOT_DEVICE_MMC2) {
143                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
144                             CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
145                 if (port == 0x0)
146                         bootmode = BOOT_DEVICE_MMC1;
147         } else if (bootmode == BOOT_DEVICE_MMC1) {
148                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
149                             CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
150                 if (port == 0x1)
151                         bootmode = BOOT_DEVICE_MMC2;
152         }
153
154         return bootmode;
155 }
156
157 u32 spl_boot_device(void)
158 {
159         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
160         u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL);
161
162         if (bootindex == K3_PRIMARY_BOOTMODE)
163                 return __get_primary_bootmedia(devstat);
164         else
165                 return __get_backup_bootmedia(devstat);
166 }
167 #endif
168
169 #ifndef CONFIG_SYSRESET
170 void reset_cpu(ulong ignored)
171 {
172 }
173 #endif