1 // SPDX-License-Identifier: GPL-2.0+
3 * AM6: SoC specific initialization
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/sysfw-loader.h>
14 #include <asm/arch/sys_proto.h>
17 #include <dm/uclass-internal.h>
18 #include <dm/pinctrl.h>
19 #include <linux/soc/ti/ti_sci_protocol.h>
21 #ifdef CONFIG_SPL_BUILD
22 #ifdef CONFIG_K3_LOAD_SYSFW
23 #ifdef CONFIG_TI_SECURE_DEVICE
24 struct fwl_data main_cbass_fwls[] = {
25 { "MMCSD1_CFG", 2057, 1 },
26 { "MMCSD0_CFG", 2058, 1 },
27 { "USB3SS0_SLV0", 2176, 2 },
28 { "PCIE0_SLV", 2336, 8 },
29 { "PCIE1_SLV", 2337, 8 },
30 { "PCIE0_CFG", 2688, 1 },
31 { "PCIE1_CFG", 2689, 1 },
32 }, mcu_cbass_fwls[] = {
33 { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
34 { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
35 { "MCU_FSS0_S1", 1033, 8 },
36 { "MCU_FSS0_S0", 1036, 8 },
37 { "MCU_CPSW0", 1220, 1 },
42 static void mmr_unlock(u32 base, u32 partition)
44 /* Translate the base address */
45 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
47 /* Unlock the requested partition if locked using two-step sequence */
48 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
49 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
52 static void ctrl_mmr_unlock(void)
54 /* Unlock all WKUP_CTRL_MMR0 module registers */
55 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
56 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
57 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
58 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
59 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
60 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
62 /* Unlock all MCU_CTRL_MMR0 module registers */
63 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
64 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
65 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
66 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
68 /* Unlock all CTRL_MMR0 module registers */
69 mmr_unlock(CTRL_MMR0_BASE, 0);
70 mmr_unlock(CTRL_MMR0_BASE, 1);
71 mmr_unlock(CTRL_MMR0_BASE, 2);
72 mmr_unlock(CTRL_MMR0_BASE, 3);
73 mmr_unlock(CTRL_MMR0_BASE, 6);
74 mmr_unlock(CTRL_MMR0_BASE, 7);
78 * This uninitialized global variable would normal end up in the .bss section,
79 * but the .bss is cleared between writing and reading this variable, so move
80 * it to the .data section.
82 u32 bootindex __attribute__((section(".data")));
84 static void store_boot_index_from_rom(void)
86 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
89 void board_init_f(ulong dummy)
91 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
96 * Cannot delay this further as there is a chance that
97 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
99 store_boot_index_from_rom();
101 /* Make all control module registers accessible */
104 #ifdef CONFIG_CPU_V7R
105 disable_linefill_optimization();
106 setup_k3_mpu_regions();
109 /* Init DM early in-order to invoke system controller */
112 #ifdef CONFIG_K3_LOAD_SYSFW
114 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
115 * regardless of the result of pinctrl. Do this without probing the
116 * device, but instead by searching the device that would request the
117 * given sequence number if probed. The UART will be used by the system
118 * firmware (SYSFW) image for various purposes and SYSFW depends on us
119 * to initialize its pin settings.
121 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
123 pinctrl_select_state(dev, "default");
126 * Load, start up, and configure system controller firmware. Provide
127 * the U-Boot console init function to the SYSFW post-PM configuration
128 * callback hook, effectively switching on (or over) the console
131 k3_sysfw_loader(preloader_console_init);
133 /* Disable ROM configured firewalls right after loading sysfw */
134 #ifdef CONFIG_TI_SECURE_DEVICE
135 remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
136 remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
139 /* Prepare console output */
140 preloader_console_init();
143 /* Perform EEPROM-based board detection */
146 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
147 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
150 printf("AVS init failed: %d\n", ret);
153 #ifdef CONFIG_K3_AM654_DDRSS
154 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
156 panic("DRAM init failed: %d\n", ret);
160 u32 spl_boot_mode(const u32 boot_device)
162 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
163 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
165 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
166 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
168 /* eMMC boot0 mode is only supported for primary boot */
169 if (bootindex == K3_PRIMARY_BOOTMODE &&
170 bootmode == BOOT_DEVICE_MMC1)
171 return MMCSD_MODE_EMMCBOOT;
174 /* Everything else use filesystem if available */
175 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
176 return MMCSD_MODE_FS;
178 return MMCSD_MODE_RAW;
182 static u32 __get_backup_bootmedia(u32 devstat)
184 u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
185 CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
188 case BACKUP_BOOT_DEVICE_USB:
189 return BOOT_DEVICE_USB;
190 case BACKUP_BOOT_DEVICE_UART:
191 return BOOT_DEVICE_UART;
192 case BACKUP_BOOT_DEVICE_ETHERNET:
193 return BOOT_DEVICE_ETHERNET;
194 case BACKUP_BOOT_DEVICE_MMC2:
196 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
197 CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
199 return BOOT_DEVICE_MMC1;
200 return BOOT_DEVICE_MMC2;
202 case BACKUP_BOOT_DEVICE_SPI:
203 return BOOT_DEVICE_SPI;
204 case BACKUP_BOOT_DEVICE_HYPERFLASH:
205 return BOOT_DEVICE_HYPERFLASH;
206 case BACKUP_BOOT_DEVICE_I2C:
207 return BOOT_DEVICE_I2C;
210 return BOOT_DEVICE_RAM;
213 static u32 __get_primary_bootmedia(u32 devstat)
215 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
216 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
218 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
219 bootmode = BOOT_DEVICE_SPI;
221 if (bootmode == BOOT_DEVICE_MMC2) {
222 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
223 CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
225 bootmode = BOOT_DEVICE_MMC1;
226 } else if (bootmode == BOOT_DEVICE_MMC1) {
227 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
228 CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
230 bootmode = BOOT_DEVICE_MMC2;
236 u32 spl_boot_device(void)
238 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
240 if (bootindex == K3_PRIMARY_BOOTMODE)
241 return __get_primary_bootmedia(devstat);
243 return __get_backup_bootmedia(devstat);
247 #ifdef CONFIG_SYS_K3_SPL_ATF
249 #define AM6_DEV_MCU_RTI0 134
250 #define AM6_DEV_MCU_RTI1 135
251 #define AM6_DEV_MCU_ARMSS0_CPU0 159
252 #define AM6_DEV_MCU_ARMSS0_CPU1 245
254 void release_resources_for_core_shutdown(void)
256 struct ti_sci_handle *ti_sci = get_ti_sci_handle();
257 struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
258 struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
262 const u32 put_device_ids[] = {
267 /* Iterate through list of devices to put (shutdown) */
268 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
269 u32 id = put_device_ids[i];
271 ret = dev_ops->put_device(ti_sci, id);
273 panic("Failed to put device %u (%d)\n", id, ret);
276 const u32 put_core_ids[] = {
277 AM6_DEV_MCU_ARMSS0_CPU1,
278 AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
281 /* Iterate through list of cores to put (shutdown) */
282 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
283 u32 id = put_core_ids[i];
286 * Queue up the core shutdown request. Note that this call
287 * needs to be followed up by an actual invocation of an WFE
288 * or WFI CPU instruction.
290 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
292 panic("Failed sending core %u shutdown message (%d)\n",