arch/arm/mach-k3/am6_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * K3: Architecture initialization
   4  *
   5  * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <spl.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/sysfw-loader.h>
  14 #include "common.h"
  15 #include <dm.h>
  16 #include <dm/uclass-internal.h>
  17 #include <dm/pinctrl.h>
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 static void mmr_unlock(u32 base, u32 partition)
  21 {
  22         /* Translate the base address */
  23         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  24
  25         /* Unlock the requested partition if locked using two-step sequence */
  26         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  27         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  28 }
  29
  30 static void ctrl_mmr_unlock(void)
  31 {
  32         /* Unlock all WKUP_CTRL_MMR0 module registers */
  33         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  34         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  35         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  36         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  37         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  38         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  39
  40         /* Unlock all MCU_CTRL_MMR0 module registers */
  41         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  42         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  43         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  44         mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  45
  46         /* Unlock all CTRL_MMR0 module registers */
  47         mmr_unlock(CTRL_MMR0_BASE, 0);
  48         mmr_unlock(CTRL_MMR0_BASE, 1);
  49         mmr_unlock(CTRL_MMR0_BASE, 2);
  50         mmr_unlock(CTRL_MMR0_BASE, 3);
  51         mmr_unlock(CTRL_MMR0_BASE, 6);
  52         mmr_unlock(CTRL_MMR0_BASE, 7);
  53 }
  54
  55 /*
  56  * This uninitialized global variable would normal end up in the .bss section,
  57  * but the .bss is cleared between writing and reading this variable, so move
  58  * it to the .data section.
  59  */
  60 u32 bootindex __attribute__((section(".data")));
  61
  62 static void store_boot_index_from_rom(void)
  63 {
  64         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  65 }
  66
  67 void board_init_f(ulong dummy)
  68 {
  69 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
  70         struct udevice *dev;
  71         int ret;
  72 #endif
  73         /*
  74          * Cannot delay this further as there is a chance that
  75          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  76          */
  77         store_boot_index_from_rom();
  78
  79         /* Make all control module registers accessible */
  80         ctrl_mmr_unlock();
  81
  82 #ifdef CONFIG_CPU_V7R
  83         setup_k3_mpu_regions();
  84 #endif
  85
  86         /* Init DM early in-order to invoke system controller */
  87         spl_early_init();
  88
  89 #ifdef CONFIG_K3_LOAD_SYSFW
  90         /*
  91          * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
  92          * regardless of the result of pinctrl. Do this without probing the
  93          * device, but instead by searching the device that would request the
  94          * given sequence number if probed. The UART will be used by the system
  95          * firmware (SYSFW) image for various purposes and SYSFW depends on us
  96          * to initialize its pin settings.
  97          */
  98         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
  99         if (!ret)
 100                 pinctrl_select_state(dev, "default");
 101
 102         /*
 103          * Load, start up, and configure system controller firmware. Provide
 104          * the U-Boot console init function to the SYSFW post-PM configuration
 105          * callback hook, effectively switching on (or over) the console
 106          * output.
 107          */
 108         k3_sysfw_loader(preloader_console_init);
 109 #else
 110         /* Prepare console output */
 111         preloader_console_init();
 112 #endif
 113
 114 #ifdef CONFIG_K3_AM654_DDRSS
 115         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 116         if (ret)
 117                 panic("DRAM init failed: %d\n", ret);
 118 #endif
 119 }
 120
 121 u32 spl_boot_mode(const u32 boot_device)
 122 {
 123 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
 124         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 125
 126         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 127                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 128
 129         /* eMMC boot0 mode is only supported for primary boot */
 130         if (bootindex == K3_PRIMARY_BOOTMODE &&
 131             bootmode == BOOT_DEVICE_MMC1)
 132                 return MMCSD_MODE_EMMCBOOT;
 133 #endif
 134
 135         /* Everything else use filesystem if available */
 136 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 137         return MMCSD_MODE_FS;
 138 #else
 139         return MMCSD_MODE_RAW;
 140 #endif
 141 }
 142
 143 static u32 __get_backup_bootmedia(u32 devstat)
 144 {
 145         u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 146                         CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 147
 148         switch (bkup_boot) {
 149         case BACKUP_BOOT_DEVICE_USB:
 150                 return BOOT_DEVICE_USB;
 151         case BACKUP_BOOT_DEVICE_UART:
 152                 return BOOT_DEVICE_UART;
 153         case BACKUP_BOOT_DEVICE_ETHERNET:
 154                 return BOOT_DEVICE_ETHERNET;
 155         case BACKUP_BOOT_DEVICE_MMC2:
 156         {
 157                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 158                             CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 159                 if (port == 0x0)
 160                         return BOOT_DEVICE_MMC1;
 161                 return BOOT_DEVICE_MMC2;
 162         }
 163         case BACKUP_BOOT_DEVICE_SPI:
 164                 return BOOT_DEVICE_SPI;
 165         case BACKUP_BOOT_DEVICE_HYPERFLASH:
 166                 return BOOT_DEVICE_HYPERFLASH;
 167         case BACKUP_BOOT_DEVICE_I2C:
 168                 return BOOT_DEVICE_I2C;
 169         };
 170
 171         return BOOT_DEVICE_RAM;
 172 }
 173
 174 static u32 __get_primary_bootmedia(u32 devstat)
 175 {
 176         u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
 177                         CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
 178
 179         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 180                 bootmode = BOOT_DEVICE_SPI;
 181
 182         if (bootmode == BOOT_DEVICE_MMC2) {
 183                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
 184                             CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
 185                 if (port == 0x0)
 186                         bootmode = BOOT_DEVICE_MMC1;
 187         } else if (bootmode == BOOT_DEVICE_MMC1) {
 188                 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
 189                             CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
 190                 if (port == 0x1)
 191                         bootmode = BOOT_DEVICE_MMC2;
 192         }
 193
 194         return bootmode;
 195 }
 196
 197 u32 spl_boot_device(void)
 198 {
 199         u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 200
 201         if (bootindex == K3_PRIMARY_BOOTMODE)
 202                 return __get_primary_bootmedia(devstat);
 203         else
 204                 return __get_backup_bootmedia(devstat);
 205 }
 206 #endif
 207
 208 #ifndef CONFIG_SYSRESET
 209 void reset_cpu(ulong ignored)
 210 {
 211 }
 212 #endif