arch/arm/mach-imx/mx7ulp/scg.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <div64.h>
   8 #include <log.h>
   9 #include <asm/io.h>
  10 #include <errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/pcc.h>
  13 #include <asm/arch/sys_proto.h>
  14
  15 scg_p scg1_regs = (scg_p)SCG1_RBASE;
  16
  17 static u32 scg_src_get_rate(enum scg_clk clksrc)
  18 {
  19         u32 reg;
  20
  21         switch (clksrc) {
  22         case SCG_SOSC_CLK:
  23                 reg = readl(&scg1_regs->sosccsr);
  24                 if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
  25                         return 0;
  26
  27                 return 24000000;
  28         case SCG_FIRC_CLK:
  29                 reg = readl(&scg1_regs->firccsr);
  30                 if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
  31                         return 0;
  32
  33                 return 48000000;
  34         case SCG_SIRC_CLK:
  35                 reg = readl(&scg1_regs->sirccsr);
  36                 if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
  37                         return 0;
  38
  39                 return 16000000;
  40         case SCG_ROSC_CLK:
  41                 reg = readl(&scg1_regs->rtccsr);
  42                 if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK))
  43                         return 0;
  44
  45                 return 32768;
  46         default:
  47                 break;
  48         }
  49
  50         return 0;
  51 }
  52
  53 static u32 scg_sircdiv_get_rate(enum scg_clk clk)
  54 {
  55         u32 reg, val, rate;
  56         u32 shift, mask;
  57
  58         switch (clk) {
  59         case SCG_SIRC_DIV1_CLK:
  60                 mask = SCG_SIRCDIV_DIV1_MASK;
  61                 shift = SCG_SIRCDIV_DIV1_SHIFT;
  62                 break;
  63         case SCG_SIRC_DIV2_CLK:
  64                 mask = SCG_SIRCDIV_DIV2_MASK;
  65                 shift = SCG_SIRCDIV_DIV2_SHIFT;
  66                 break;
  67         case SCG_SIRC_DIV3_CLK:
  68                 mask = SCG_SIRCDIV_DIV3_MASK;
  69                 shift = SCG_SIRCDIV_DIV3_SHIFT;
  70                 break;
  71         default:
  72                 return 0;
  73         }
  74
  75         reg = readl(&scg1_regs->sirccsr);
  76         if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
  77                 return 0;
  78
  79         reg = readl(&scg1_regs->sircdiv);
  80         val = (reg & mask) >> shift;
  81
  82         if (!val) /*clock disabled*/
  83                 return 0;
  84
  85         rate = scg_src_get_rate(SCG_SIRC_CLK);
  86         rate = rate / (1 << (val - 1));
  87
  88         return rate;
  89 }
  90
  91 static u32 scg_fircdiv_get_rate(enum scg_clk clk)
  92 {
  93         u32 reg, val, rate;
  94         u32 shift, mask;
  95
  96         switch (clk) {
  97         case SCG_FIRC_DIV1_CLK:
  98                 mask = SCG_FIRCDIV_DIV1_MASK;
  99                 shift = SCG_FIRCDIV_DIV1_SHIFT;
 100                 break;
 101         case SCG_FIRC_DIV2_CLK:
 102                 mask = SCG_FIRCDIV_DIV2_MASK;
 103                 shift = SCG_FIRCDIV_DIV2_SHIFT;
 104                 break;
 105         case SCG_FIRC_DIV3_CLK:
 106                 mask = SCG_FIRCDIV_DIV3_MASK;
 107                 shift = SCG_FIRCDIV_DIV3_SHIFT;
 108                 break;
 109         default:
 110                 return 0;
 111         }
 112
 113         reg = readl(&scg1_regs->firccsr);
 114         if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
 115                 return 0;
 116
 117         reg = readl(&scg1_regs->fircdiv);
 118         val = (reg & mask) >> shift;
 119
 120         if (!val) /*clock disabled*/
 121                 return 0;
 122
 123         rate = scg_src_get_rate(SCG_FIRC_CLK);
 124         rate = rate / (1 << (val - 1));
 125
 126         return rate;
 127 }
 128
 129 static u32 scg_soscdiv_get_rate(enum scg_clk clk)
 130 {
 131         u32 reg, val, rate;
 132         u32 shift, mask;
 133
 134         switch (clk) {
 135         case SCG_SOSC_DIV1_CLK:
 136                 mask = SCG_SOSCDIV_DIV1_MASK;
 137                 shift = SCG_SOSCDIV_DIV1_SHIFT;
 138                 break;
 139         case SCG_SOSC_DIV2_CLK:
 140                 mask = SCG_SOSCDIV_DIV2_MASK;
 141                 shift = SCG_SOSCDIV_DIV2_SHIFT;
 142                 break;
 143         case SCG_SOSC_DIV3_CLK:
 144                 mask = SCG_SOSCDIV_DIV3_MASK;
 145                 shift = SCG_SOSCDIV_DIV3_SHIFT;
 146                 break;
 147         default:
 148                 return 0;
 149         }
 150
 151         reg = readl(&scg1_regs->sosccsr);
 152         if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
 153                 return 0;
 154
 155         reg = readl(&scg1_regs->soscdiv);
 156         val = (reg & mask) >> shift;
 157
 158         if (!val) /*clock disabled*/
 159                 return 0;
 160
 161         rate = scg_src_get_rate(SCG_SOSC_CLK);
 162         rate = rate / (1 << (val - 1));
 163
 164         return rate;
 165 }
 166
 167 static u32 scg_apll_pfd_get_rate(enum scg_clk clk)
 168 {
 169         u32 reg, val, rate;
 170         u32 shift, mask, gate, valid;
 171
 172         switch (clk) {
 173         case SCG_APLL_PFD0_CLK:
 174                 gate = SCG_PLL_PFD0_GATE_MASK;
 175                 valid = SCG_PLL_PFD0_VALID_MASK;
 176                 mask = SCG_PLL_PFD0_FRAC_MASK;
 177                 shift = SCG_PLL_PFD0_FRAC_SHIFT;
 178                 break;
 179         case SCG_APLL_PFD1_CLK:
 180                 gate = SCG_PLL_PFD1_GATE_MASK;
 181                 valid = SCG_PLL_PFD1_VALID_MASK;
 182                 mask = SCG_PLL_PFD1_FRAC_MASK;
 183                 shift = SCG_PLL_PFD1_FRAC_SHIFT;
 184                 break;
 185         case SCG_APLL_PFD2_CLK:
 186                 gate = SCG_PLL_PFD2_GATE_MASK;
 187                 valid = SCG_PLL_PFD2_VALID_MASK;
 188                 mask = SCG_PLL_PFD2_FRAC_MASK;
 189                 shift = SCG_PLL_PFD2_FRAC_SHIFT;
 190                 break;
 191         case SCG_APLL_PFD3_CLK:
 192                 gate = SCG_PLL_PFD3_GATE_MASK;
 193                 valid = SCG_PLL_PFD3_VALID_MASK;
 194                 mask = SCG_PLL_PFD3_FRAC_MASK;
 195                 shift = SCG_PLL_PFD3_FRAC_SHIFT;
 196                 break;
 197         default:
 198                 return 0;
 199         }
 200
 201         reg = readl(&scg1_regs->apllpfd);
 202         if (reg & gate || !(reg & valid))
 203                 return 0;
 204
 205         clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg);
 206
 207         val = (reg & mask) >> shift;
 208         rate = decode_pll(PLL_A7_APLL);
 209
 210         rate = rate / val * 18;
 211
 212         clk_debug("scg_apll_pfd_get_rate rate %u\n", rate);
 213
 214         return rate;
 215 }
 216
 217 static u32 scg_spll_pfd_get_rate(enum scg_clk clk)
 218 {
 219         u32 reg, val, rate;
 220         u32 shift, mask, gate, valid;
 221
 222         switch (clk) {
 223         case SCG_SPLL_PFD0_CLK:
 224                 gate = SCG_PLL_PFD0_GATE_MASK;
 225                 valid = SCG_PLL_PFD0_VALID_MASK;
 226                 mask = SCG_PLL_PFD0_FRAC_MASK;
 227                 shift = SCG_PLL_PFD0_FRAC_SHIFT;
 228                 break;
 229         case SCG_SPLL_PFD1_CLK:
 230                 gate = SCG_PLL_PFD1_GATE_MASK;
 231                 valid = SCG_PLL_PFD1_VALID_MASK;
 232                 mask = SCG_PLL_PFD1_FRAC_MASK;
 233                 shift = SCG_PLL_PFD1_FRAC_SHIFT;
 234                 break;
 235         case SCG_SPLL_PFD2_CLK:
 236                 gate = SCG_PLL_PFD2_GATE_MASK;
 237                 valid = SCG_PLL_PFD2_VALID_MASK;
 238                 mask = SCG_PLL_PFD2_FRAC_MASK;
 239                 shift = SCG_PLL_PFD2_FRAC_SHIFT;
 240                 break;
 241         case SCG_SPLL_PFD3_CLK:
 242                 gate = SCG_PLL_PFD3_GATE_MASK;
 243                 valid = SCG_PLL_PFD3_VALID_MASK;
 244                 mask = SCG_PLL_PFD3_FRAC_MASK;
 245                 shift = SCG_PLL_PFD3_FRAC_SHIFT;
 246                 break;
 247         default:
 248                 return 0;
 249         }
 250
 251         reg = readl(&scg1_regs->spllpfd);
 252         if (reg & gate || !(reg & valid))
 253                 return 0;
 254
 255         clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg);
 256
 257         val = (reg & mask) >> shift;
 258         rate = decode_pll(PLL_A7_SPLL);
 259
 260         rate = rate / val * 18;
 261
 262         clk_debug("scg_spll_pfd_get_rate rate %u\n", rate);
 263
 264         return rate;
 265 }
 266
 267 static u32 scg_apll_get_rate(void)
 268 {
 269         u32 reg, val, rate;
 270
 271         reg = readl(&scg1_regs->apllcfg);
 272         val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
 273
 274         if (!val) {
 275                 /* APLL clock after two dividers */
 276                 rate = decode_pll(PLL_A7_APLL);
 277
 278                 val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
 279                         SCG_PLL_CFG_POSTDIV1_SHIFT;
 280                 rate = rate / (val + 1);
 281
 282                 val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
 283                         SCG_PLL_CFG_POSTDIV2_SHIFT;
 284                 rate = rate / (val + 1);
 285         } else {
 286                 /* APLL PFD clock */
 287                 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
 288                         SCG_PLL_CFG_PFDSEL_SHIFT;
 289                 rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
 290         }
 291
 292         return rate;
 293 }
 294
 295 static u32 scg_spll_get_rate(void)
 296 {
 297         u32 reg, val, rate;
 298
 299         reg = readl(&scg1_regs->spllcfg);
 300         val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
 301
 302         clk_debug("scg_spll_get_rate reg 0x%x\n", reg);
 303
 304         if (!val) {
 305                 /* APLL clock after two dividers */
 306                 rate = decode_pll(PLL_A7_SPLL);
 307
 308                 val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
 309                         SCG_PLL_CFG_POSTDIV1_SHIFT;
 310                 rate = rate / (val + 1);
 311
 312                 val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
 313                         SCG_PLL_CFG_POSTDIV2_SHIFT;
 314                 rate = rate / (val + 1);
 315
 316                 clk_debug("scg_spll_get_rate SPLL %u\n", rate);
 317
 318         } else {
 319                 /* APLL PFD clock */
 320                 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
 321                         SCG_PLL_CFG_PFDSEL_SHIFT;
 322                 rate = scg_spll_pfd_get_rate(SCG_SPLL_PFD0_CLK + val);
 323
 324                 clk_debug("scg_spll_get_rate PFD %u\n", rate);
 325         }
 326
 327         return rate;
 328 }
 329
 330 static u32 scg_ddr_get_rate(void)
 331 {
 332         u32 reg, val, rate, div;
 333
 334         reg = readl(&scg1_regs->ddrccr);
 335         val = (reg & SCG_DDRCCR_DDRCS_MASK) >> SCG_DDRCCR_DDRCS_SHIFT;
 336         div = (reg & SCG_DDRCCR_DDRDIV_MASK) >> SCG_DDRCCR_DDRDIV_SHIFT;
 337
 338         if (!div)
 339                 return 0;
 340
 341         if (!val) {
 342                 reg = readl(&scg1_regs->apllcfg);
 343                 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
 344                         SCG_PLL_CFG_PFDSEL_SHIFT;
 345                 rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
 346         } else {
 347                 rate = decode_pll(PLL_USB);
 348         }
 349
 350         rate = rate / (1 << (div - 1));
 351         return rate;
 352 }
 353
 354 static u32 scg_nic_get_rate(enum scg_clk clk)
 355 {
 356         u32 reg, val, rate, nic0_rate;
 357         u32 shift, mask;
 358
 359         reg = readl(&scg1_regs->niccsr);
 360         val = (reg & SCG_NICCSR_NICCS_MASK) >> SCG_NICCSR_NICCS_SHIFT;
 361
 362         clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg);
 363
 364         if (!val)
 365                 rate = scg_src_get_rate(SCG_FIRC_CLK);
 366         else
 367                 rate = scg_ddr_get_rate();
 368
 369         clk_debug("scg_nic_get_rate parent rate %u\n", rate);
 370
 371         val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT;
 372
 373         rate = rate / (val + 1);
 374         nic0_rate = rate;
 375
 376         clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate);
 377
 378         switch (clk) {
 379         case SCG_NIC0_CLK:
 380                 return rate;
 381         case SCG_GPU_CLK:
 382                 mask = SCG_NICCSR_GPUDIV_MASK;
 383                 shift = SCG_NICCSR_GPUDIV_SHIFT;
 384                 break;
 385         case SCG_NIC1_EXT_CLK:
 386         case SCG_NIC1_BUS_CLK:
 387         case SCG_NIC1_CLK:
 388                 mask = SCG_NICCSR_NIC1DIV_MASK;
 389                 shift = SCG_NICCSR_NIC1DIV_SHIFT;
 390                 break;
 391         default:
 392                 return 0;
 393         }
 394
 395         val = (reg & mask) >> shift;
 396         rate = rate / (val + 1);
 397
 398         clk_debug("scg_nic_get_rate NIC1 rate %u\n", rate);
 399
 400         switch (clk) {
 401         case SCG_GPU_CLK:
 402         case SCG_NIC1_CLK:
 403                 return rate;
 404         case SCG_NIC1_EXT_CLK:
 405                 mask = SCG_NICCSR_NIC1EXTDIV_MASK;
 406                 shift = SCG_NICCSR_NIC1EXTDIV_SHIFT;
 407                 break;
 408         case SCG_NIC1_BUS_CLK:
 409                 mask = SCG_NICCSR_NIC1BUSDIV_MASK;
 410                 shift = SCG_NICCSR_NIC1BUSDIV_SHIFT;
 411                 break;
 412         default:
 413                 return 0;
 414         }
 415
 416         /*
 417          * On RevB, the nic_bus and nic_ext dividers are parallel
 418          * not chained with nic div
 419          */
 420         if (soc_rev() >= CHIP_REV_2_0)
 421                 rate = nic0_rate;
 422
 423         val = (reg & mask) >> shift;
 424         rate = rate / (val + 1);
 425
 426         clk_debug("scg_nic_get_rate NIC1 bus rate %u\n", rate);
 427         return rate;
 428 }
 429
 430
 431 static enum scg_clk scg_scs_array[4] = {
 432         SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK,
 433 };
 434
 435 static u32 scg_sys_get_rate(enum scg_clk clk)
 436 {
 437         u32 reg, val, rate;
 438
 439         if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK)
 440                 return 0;
 441
 442         reg = readl(&scg1_regs->csr);
 443         val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT;
 444
 445         clk_debug("scg_sys_get_rate reg 0x%x\n", reg);
 446
 447         switch (val) {
 448         case SCG_SCS_SYS_OSC:
 449         case SCG_SCS_SLOW_IRC:
 450         case SCG_SCS_FAST_IRC:
 451         case SCG_SCS_RTC_OSC:
 452                 rate = scg_src_get_rate(scg_scs_array[val - 1]);
 453                 break;
 454         case 5:
 455                 rate = scg_apll_get_rate();
 456                 break;
 457         case 6:
 458                 rate = scg_spll_get_rate();
 459                 break;
 460         default:
 461                 return 0;
 462         }
 463
 464         clk_debug("scg_sys_get_rate parent rate %u\n", rate);
 465
 466         val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT;
 467
 468         rate = rate / (val + 1);
 469
 470         if (clk == SCG_BUS_CLK) {
 471                 val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT;
 472                 rate = rate / (val + 1);
 473         }
 474
 475         return rate;
 476 }
 477
 478 u32 decode_pll(enum pll_clocks pll)
 479 {
 480         u32 reg,  pre_div, infreq, mult;
 481         u32 num, denom;
 482
 483         /*
 484          * Alought there are four choices for the bypass src,
 485          * we choose OSC_24M which is the default set in ROM.
 486          */
 487         switch (pll) {
 488         case PLL_A7_SPLL:
 489                 reg = readl(&scg1_regs->spllcsr);
 490
 491                 if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK))
 492                         return 0;
 493
 494                 reg = readl(&scg1_regs->spllcfg);
 495
 496                 pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
 497                            SCG_PLL_CFG_PREDIV_SHIFT;
 498                 pre_div += 1;
 499
 500                 mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >>
 501                            SCG_PLL_CFG_MULT_SHIFT;
 502
 503                 infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
 504                            SCG_PLL_CFG_CLKSRC_SHIFT;
 505                 if (!infreq)
 506                         infreq = scg_src_get_rate(SCG_SOSC_CLK);
 507                 else
 508                         infreq = scg_src_get_rate(SCG_FIRC_CLK);
 509
 510                 num = readl(&scg1_regs->spllnum);
 511                 denom = readl(&scg1_regs->splldenom);
 512
 513                 infreq = infreq / pre_div;
 514
 515                 if (denom)
 516                         return infreq * mult + infreq * num / denom;
 517                 else
 518                         return infreq * mult;
 519
 520         case PLL_A7_APLL:
 521                 reg = readl(&scg1_regs->apllcsr);
 522
 523                 if (!(reg & SCG_APLL_CSR_APLLVLD_MASK))
 524                         return 0;
 525
 526                 reg = readl(&scg1_regs->apllcfg);
 527
 528                 pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
 529                            SCG_PLL_CFG_PREDIV_SHIFT;
 530                 pre_div += 1;
 531
 532                 mult = (reg & SCG_APLL_CFG_MULT_MASK) >>
 533                            SCG_PLL_CFG_MULT_SHIFT;
 534
 535                 infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
 536                            SCG_PLL_CFG_CLKSRC_SHIFT;
 537                 if (!infreq)
 538                         infreq = scg_src_get_rate(SCG_SOSC_CLK);
 539                 else
 540                         infreq = scg_src_get_rate(SCG_FIRC_CLK);
 541
 542                 num = readl(&scg1_regs->apllnum);
 543                 denom = readl(&scg1_regs->aplldenom);
 544
 545                 infreq = infreq / pre_div;
 546
 547                 if (denom)
 548                         return infreq * mult + infreq * num / denom;
 549                 else
 550                         return infreq * mult;
 551
 552         case PLL_USB:
 553                 reg = readl(&scg1_regs->upllcsr);
 554
 555                 if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK))
 556                         return 0;
 557
 558                 return 480000000u;
 559
 560         case PLL_MIPI:
 561                 return 480000000u;
 562         default:
 563                 printf("Unsupported pll clocks %d\n", pll);
 564                 break;
 565         }
 566
 567         return 0;
 568 }
 569
 570 u32 scg_clk_get_rate(enum scg_clk clk)
 571 {
 572         switch (clk) {
 573         case SCG_SIRC_DIV1_CLK:
 574         case SCG_SIRC_DIV2_CLK:
 575         case SCG_SIRC_DIV3_CLK:
 576                 return scg_sircdiv_get_rate(clk);
 577
 578         case SCG_FIRC_DIV1_CLK:
 579         case SCG_FIRC_DIV2_CLK:
 580         case SCG_FIRC_DIV3_CLK:
 581                 return scg_fircdiv_get_rate(clk);
 582
 583         case SCG_SOSC_DIV1_CLK:
 584         case SCG_SOSC_DIV2_CLK:
 585         case SCG_SOSC_DIV3_CLK:
 586                 return scg_soscdiv_get_rate(clk);
 587
 588         case SCG_CORE_CLK:
 589         case SCG_BUS_CLK:
 590                 return scg_sys_get_rate(clk);
 591
 592         case SCG_SPLL_PFD0_CLK:
 593         case SCG_SPLL_PFD1_CLK:
 594         case SCG_SPLL_PFD2_CLK:
 595         case SCG_SPLL_PFD3_CLK:
 596                 return scg_spll_pfd_get_rate(clk);
 597
 598         case SCG_APLL_PFD0_CLK:
 599         case SCG_APLL_PFD1_CLK:
 600         case SCG_APLL_PFD2_CLK:
 601         case SCG_APLL_PFD3_CLK:
 602                 return scg_apll_pfd_get_rate(clk);
 603
 604         case SCG_DDR_CLK:
 605                 return scg_ddr_get_rate();
 606
 607         case SCG_NIC0_CLK:
 608         case SCG_GPU_CLK:
 609         case SCG_NIC1_CLK:
 610         case SCG_NIC1_BUS_CLK:
 611         case SCG_NIC1_EXT_CLK:
 612                 return scg_nic_get_rate(clk);
 613
 614         case USB_PLL_OUT:
 615                 return decode_pll(PLL_USB);
 616
 617         case MIPI_PLL_OUT:
 618                 return decode_pll(PLL_MIPI);
 619
 620         case SCG_SOSC_CLK:
 621         case SCG_FIRC_CLK:
 622         case SCG_SIRC_CLK:
 623         case SCG_ROSC_CLK:
 624                 return scg_src_get_rate(clk);
 625         default:
 626                 return 0;
 627         }
 628 }
 629
 630 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac)
 631 {
 632         u32 reg;
 633         u32 shift, mask, gate, valid;
 634         u32 addr;
 635
 636         if (frac < 12 || frac > 35)
 637                 return -EINVAL;
 638
 639         switch (clk) {
 640         case SCG_SPLL_PFD0_CLK:
 641         case SCG_APLL_PFD0_CLK:
 642                 gate = SCG_PLL_PFD0_GATE_MASK;
 643                 valid = SCG_PLL_PFD0_VALID_MASK;
 644                 mask = SCG_PLL_PFD0_FRAC_MASK;
 645                 shift = SCG_PLL_PFD0_FRAC_SHIFT;
 646
 647                 if (clk == SCG_SPLL_PFD0_CLK)
 648                         addr = (u32)(&scg1_regs->spllpfd);
 649                 else
 650                         addr = (u32)(&scg1_regs->apllpfd);
 651                 break;
 652         case SCG_SPLL_PFD1_CLK:
 653         case SCG_APLL_PFD1_CLK:
 654                 gate = SCG_PLL_PFD1_GATE_MASK;
 655                 valid = SCG_PLL_PFD1_VALID_MASK;
 656                 mask = SCG_PLL_PFD1_FRAC_MASK;
 657                 shift = SCG_PLL_PFD1_FRAC_SHIFT;
 658
 659                 if (clk == SCG_SPLL_PFD1_CLK)
 660                         addr = (u32)(&scg1_regs->spllpfd);
 661                 else
 662                         addr = (u32)(&scg1_regs->apllpfd);
 663                 break;
 664         case SCG_SPLL_PFD2_CLK:
 665         case SCG_APLL_PFD2_CLK:
 666                 gate = SCG_PLL_PFD2_GATE_MASK;
 667                 valid = SCG_PLL_PFD2_VALID_MASK;
 668                 mask = SCG_PLL_PFD2_FRAC_MASK;
 669                 shift = SCG_PLL_PFD2_FRAC_SHIFT;
 670
 671                 if (clk == SCG_SPLL_PFD2_CLK)
 672                         addr = (u32)(&scg1_regs->spllpfd);
 673                 else
 674                         addr = (u32)(&scg1_regs->apllpfd);
 675                 break;
 676         case SCG_SPLL_PFD3_CLK:
 677         case SCG_APLL_PFD3_CLK:
 678                 gate = SCG_PLL_PFD3_GATE_MASK;
 679                 valid = SCG_PLL_PFD3_VALID_MASK;
 680                 mask = SCG_PLL_PFD3_FRAC_MASK;
 681                 shift = SCG_PLL_PFD3_FRAC_SHIFT;
 682
 683                 if (clk == SCG_SPLL_PFD3_CLK)
 684                         addr = (u32)(&scg1_regs->spllpfd);
 685                 else
 686                         addr = (u32)(&scg1_regs->apllpfd);
 687                 break;
 688         default:
 689                 return -EINVAL;
 690         }
 691
 692         /* Gate the PFD */
 693         reg = readl(addr);
 694         reg |= gate;
 695         writel(reg, addr);
 696
 697         /* Write Frac divider */
 698         reg &= ~mask;
 699         reg |= (frac << shift) & mask;
 700         writel(reg, addr);
 701
 702         /*
 703          * Un-gate the PFD
 704          * (Need un-gate before checking valid, not align with RM)
 705          */
 706         reg &= ~gate;
 707         writel(reg, addr);
 708
 709         /* Wait for PFD clock being valid */
 710         do {
 711                 reg = readl(addr);
 712         } while (!(reg & valid));
 713
 714         return 0;
 715 }
 716
 717 #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
 718 int scg_enable_usb_pll(bool usb_control)
 719 {
 720         u32 sosc_rate;
 721         s32 timeout = 1000000;
 722         u32 reg;
 723
 724         struct usbphy_regs *usbphy =
 725                 (struct usbphy_regs *)USBPHY_RBASE;
 726
 727         sosc_rate = scg_src_get_rate(SCG_SOSC_CLK);
 728         if (!sosc_rate)
 729                 return -EPERM;
 730
 731         reg = readl(SIM0_RBASE + 0x3C);
 732         if (usb_control)
 733                 reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
 734         else
 735                 reg |= SIM_MISC_CTRL0_USB_PLL_EN_MASK;
 736         writel(reg, SIM0_RBASE + 0x3C);
 737
 738         if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {
 739                 writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr);
 740
 741                 switch (sosc_rate) {
 742                 case 24000000:
 743                         writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
 744                         break;
 745
 746                 case 30000000:
 747                         writel(0x800000, &usbphy->usb1_pll_480_ctrl_set);
 748                         break;
 749
 750                 case 19200000:
 751                         writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set);
 752                         break;
 753
 754                 default:
 755                         writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
 756                         break;
 757                 }
 758
 759                 /* Enable the regulator first */
 760                 writel(PLL_USB_REG_ENABLE_MASK,
 761                        &usbphy->usb1_pll_480_ctrl_set);
 762
 763                 /* Wait at least 15us */
 764                 udelay(15);
 765
 766                 /* Enable the power */
 767                 writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);
 768
 769                 /* Wait lock */
 770                 while (timeout--) {
 771                         if (readl(&usbphy->usb1_pll_480_ctrl) &
 772                             PLL_USB_LOCK_MASK)
 773                                 break;
 774                 }
 775
 776                 if (timeout <= 0) {
 777                         /* If timeout, we power down the pll */
 778                         writel(PLL_USB_PWR_MASK,
 779                                &usbphy->usb1_pll_480_ctrl_clr);
 780                         return -ETIME;
 781                 }
 782         }
 783
 784         /* Clear the bypass */
 785         writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);
 786
 787         /* Enable the PLL clock out to USB */
 788         writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK),
 789                &usbphy->usb1_pll_480_ctrl_set);
 790
 791         if (!usb_control) {
 792                 while (timeout--) {
 793                         if (readl(&scg1_regs->upllcsr) &
 794                             SCG_UPLL_CSR_UPLLVLD_MASK)
 795                                 break;
 796                 }
 797
 798                 if (timeout <= 0) {
 799                         reg = readl(SIM0_RBASE + 0x3C);
 800                         reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
 801                         writel(reg, SIM0_RBASE + 0x3C);
 802                         return -ETIME;
 803                 }
 804         }
 805
 806         return 0;
 807 }
 808
 809
 810 /* A7 domain system clock source is SPLL */
 811 #define SCG1_RCCR_SCS_NUM       ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT)
 812
 813 /* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */
 814 #define SCG1_RCCR_DIVCORE_NUM   ((0x0)  << SCG_CCR_DIVCORE_SHIFT)
 815 #define SCG1_RCCR_CFG_MASK      (SCG_CCR_SCS_MASK | SCG_CCR_DIVBUS_MASK)
 816
 817 /* A7 Plat clck = A7 Core Clock / 2 = 250MHz / 1 = 250MHz */
 818 #define SCG1_RCCR_DIVBUS_NUM    ((0x1)  << SCG_CCR_DIVBUS_SHIFT)
 819 #define SCG1_RCCR_CFG_NUM       (SCG1_RCCR_SCS_NUM | SCG1_RCCR_DIVBUS_NUM)
 820
 821 void scg_a7_rccr_init(void)
 822 {
 823         u32 rccr_reg_val = 0;
 824
 825         rccr_reg_val = readl(&scg1_regs->rccr);
 826
 827         rccr_reg_val &= (~SCG1_RCCR_CFG_MASK);
 828         rccr_reg_val |= (SCG1_RCCR_CFG_NUM);
 829
 830         writel(rccr_reg_val, &scg1_regs->rccr);
 831 }
 832
 833 /* POSTDIV2 = 1 */
 834 #define SCG1_SPLL_CFG_POSTDIV2_NUM      ((0x0)  << SCG_PLL_CFG_POSTDIV2_SHIFT)
 835 /* POSTDIV1 = 1 */
 836 #define SCG1_SPLL_CFG_POSTDIV1_NUM      ((0x0)  << SCG_PLL_CFG_POSTDIV1_SHIFT)
 837
 838 /* MULT = 22 */
 839 #define SCG1_SPLL_CFG_MULT_NUM          ((22)   << SCG_PLL_CFG_MULT_SHIFT)
 840
 841 /* PFD0 output clock selected */
 842 #define SCG1_SPLL_CFG_PFDSEL_NUM        ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
 843 /* PREDIV = 1 */
 844 #define SCG1_SPLL_CFG_PREDIV_NUM        ((0x0)  << SCG_PLL_CFG_PREDIV_SHIFT)
 845 /* SPLL output clocks (including PFD outputs) selected */
 846 #define SCG1_SPLL_CFG_BYPASS_NUM        ((0x0)  << SCG_PLL_CFG_BYPASS_SHIFT)
 847 /* SPLL PFD output clock selected */
 848 #define SCG1_SPLL_CFG_PLLSEL_NUM        ((0x1)  << SCG_PLL_CFG_PLLSEL_SHIFT)
 849 /* Clock source is System OSC */
 850 #define SCG1_SPLL_CFG_CLKSRC_NUM        ((0x0)  << SCG_PLL_CFG_CLKSRC_SHIFT)
 851 #define SCG1_SPLL_CFG_NUM_24M_OSC       (SCG1_SPLL_CFG_POSTDIV2_NUM     | \
 852                                          SCG1_SPLL_CFG_POSTDIV1_NUM     | \
 853                                          (22 << SCG_PLL_CFG_MULT_SHIFT) | \
 854                                          SCG1_SPLL_CFG_PFDSEL_NUM       | \
 855                                          SCG1_SPLL_CFG_PREDIV_NUM       | \
 856                                          SCG1_SPLL_CFG_BYPASS_NUM       | \
 857                                          SCG1_SPLL_CFG_PLLSEL_NUM       | \
 858                                          SCG1_SPLL_CFG_CLKSRC_NUM)
 859 /*413Mhz = A7 SPLL(528MHz) * 18/23 */
 860 #define SCG1_SPLL_PFD0_FRAC_NUM         ((23) << SCG_PLL_PFD0_FRAC_SHIFT)
 861
 862 void scg_a7_spll_init(void)
 863 {
 864         u32 val = 0;
 865
 866         /* Disable A7 System PLL */
 867         val = readl(&scg1_regs->spllcsr);
 868         val &= ~SCG_SPLL_CSR_SPLLEN_MASK;
 869         writel(val, &scg1_regs->spllcsr);
 870
 871         /*
 872          * Per block guide,
 873          * "When changing PFD values, it is recommneded PFDx clock
 874          * gets gated first by writing a value of 1 to PFDx_CLKGATE register,
 875          * then program the new PFD value, then poll the PFDx_VALID
 876          * flag to set before writing a value of 0 to PFDx_CLKGATE
 877          * to ungate the PFDx clock and allow PFDx clock to run"
 878          */
 879
 880         /* Gate off A7 SPLL PFD0 ~ PDF4  */
 881         val = readl(&scg1_regs->spllpfd);
 882         val |= (SCG_PLL_PFD3_GATE_MASK |
 883                         SCG_PLL_PFD2_GATE_MASK |
 884                         SCG_PLL_PFD1_GATE_MASK |
 885                         SCG_PLL_PFD0_GATE_MASK);
 886         writel(val, &scg1_regs->spllpfd);
 887
 888         /* ================ A7 SPLL Configuration Start ============== */
 889
 890         /* Configure A7 System PLL */
 891         writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg);
 892
 893         /* Enable A7 System PLL */
 894         val = readl(&scg1_regs->spllcsr);
 895         val |= SCG_SPLL_CSR_SPLLEN_MASK;
 896         writel(val, &scg1_regs->spllcsr);
 897
 898         /* Wait for A7 SPLL clock ready */
 899         while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))
 900                 ;
 901
 902         /* Configure A7 SPLL PFD0 */
 903         val = readl(&scg1_regs->spllpfd);
 904         val &= ~SCG_PLL_PFD0_FRAC_MASK;
 905         val |= SCG1_SPLL_PFD0_FRAC_NUM;
 906         writel(val, &scg1_regs->spllpfd);
 907
 908         /* Un-gate A7 SPLL PFD0 */
 909         val = readl(&scg1_regs->spllpfd);
 910         val &= ~SCG_PLL_PFD0_GATE_MASK;
 911         writel(val, &scg1_regs->spllpfd);
 912
 913         /* Wait for A7 SPLL PFD0 clock being valid */
 914         while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))
 915                 ;
 916
 917         /* ================ A7 SPLL Configuration End ============== */
 918 }
 919
 920 /* DDR clock source is APLL PFD0 (396MHz) */
 921 #define SCG1_DDRCCR_DDRCS_NUM           ((0x0) << SCG_DDRCCR_DDRCS_SHIFT)
 922 /* DDR clock = APLL PFD0 / 1 = 396MHz / 1 = 396MHz */
 923 #define SCG1_DDRCCR_DDRDIV_NUM          ((0x1) << SCG_DDRCCR_DDRDIV_SHIFT)
 924 /* DDR clock = APLL PFD0 / 2 = 396MHz / 2 = 198MHz */
 925 #define SCG1_DDRCCR_DDRDIV_LF_NUM       ((0x2) << SCG_DDRCCR_DDRDIV_SHIFT)
 926 #define SCG1_DDRCCR_CFG_NUM             (SCG1_DDRCCR_DDRCS_NUM  | \
 927                                          SCG1_DDRCCR_DDRDIV_NUM)
 928 #define SCG1_DDRCCR_CFG_LF_NUM          (SCG1_DDRCCR_DDRCS_NUM  | \
 929                                          SCG1_DDRCCR_DDRDIV_LF_NUM)
 930 void scg_a7_ddrclk_init(void)
 931 {
 932         writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr);
 933 }
 934
 935 /* SCG1(A7) APLLCFG configurations */
 936 /* divide by 1 <<28 */
 937 #define SCG1_APLL_CFG_POSTDIV2_NUM      ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
 938 /* divide by 1 <<24 */
 939 #define SCG1_APLL_CFG_POSTDIV1_NUM      ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
 940 /* MULT is 22  <<16 */
 941 #define SCG1_APLL_CFG_MULT_NUM          ((22)  << SCG_PLL_CFG_MULT_SHIFT)
 942 /* PFD0 output clock selected  <<14 */
 943 #define SCG1_APLL_CFG_PFDSEL_NUM        ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
 944 /* PREDIV = 1   <<8 */
 945 #define SCG1_APLL_CFG_PREDIV_NUM        ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
 946 /* APLL output clocks (including PFD outputs) selected  <<2 */
 947 #define SCG1_APLL_CFG_BYPASS_NUM        ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
 948 /* APLL PFD output clock selected <<1 */
 949 #define SCG1_APLL_CFG_PLLSEL_NUM        ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT)
 950 /* Clock source is System OSC <<0 */
 951 #define SCG1_APLL_CFG_CLKSRC_NUM        ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
 952
 953 /* SCG1(A7) FIRC DIV configurations */
 954 /* Disable FIRC DIV3 */
 955 #define SCG1_FIRCDIV_DIV3_NUM           ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)
 956 /* FIRC DIV2 = 48MHz / 1 = 48MHz */
 957 #define SCG1_FIRCDIV_DIV2_NUM           ((0x1) << SCG_FIRCDIV_DIV2_SHIFT)
 958 /* Disable FIRC DIV1 */
 959 #define SCG1_FIRCDIV_DIV1_NUM           ((0x0) << SCG_FIRCDIV_DIV1_SHIFT)
 960
 961 void scg_a7_firc_init(void)
 962 {
 963         /* Wait for FIRC clock ready */
 964         while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))
 965                 ;
 966
 967         /* Configure A7 FIRC DIV1 ~ DIV3 */
 968         writel((SCG1_FIRCDIV_DIV3_NUM |
 969                         SCG1_FIRCDIV_DIV2_NUM |
 970                         SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv);
 971 }
 972
 973 /* SCG1(A7) NICCCR configurations */
 974 /* NIC clock source is DDR clock (396/198MHz) */
 975 #define SCG1_NICCCR_NICCS_NUM           ((0x1) << SCG_NICCCR_NICCS_SHIFT)
 976
 977 /* NIC0 clock = DDR Clock / 2 = 396MHz / 2 = 198MHz */
 978 #define SCG1_NICCCR_NIC0_DIV_NUM        ((0x1) << SCG_NICCCR_NIC0_DIV_SHIFT)
 979 /* NIC0 clock = DDR Clock / 1 = 198MHz / 1 = 198MHz */
 980 #define SCG1_NICCCR_NIC0_DIV_LF_NUM     ((0x0) << SCG_NICCCR_NIC0_DIV_SHIFT)
 981 /* NIC1 clock = NIC0 Clock / 1 = 198MHz / 2 = 198MHz */
 982 #define SCG1_NICCCR_NIC1_DIV_NUM        ((0x0) << SCG_NICCCR_NIC1_DIV_SHIFT)
 983 /* NIC1 bus clock = NIC1 Clock / 3 = 198MHz / 3 = 66MHz */
 984 #define SCG1_NICCCR_NIC1_DIVBUS_NUM     ((0x2) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
 985 #define SCG1_NICCCR_CFG_NUM             (SCG1_NICCCR_NICCS_NUM      | \
 986                                          SCG1_NICCCR_NIC0_DIV_NUM   | \
 987                                          SCG1_NICCCR_NIC1_DIV_NUM   | \
 988                                          SCG1_NICCCR_NIC1_DIVBUS_NUM)
 989
 990 void scg_a7_nicclk_init(void)
 991 {
 992         writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr);
 993 }
 994
 995 /* SCG1(A7) FIRC DIV configurations */
 996 /* Enable FIRC DIV3 */
 997 #define SCG1_SOSCDIV_DIV3_NUM           ((0x1) << SCG_SOSCDIV_DIV3_SHIFT)
 998 /* FIRC DIV2 = 48MHz / 1 = 48MHz */
 999 #define SCG1_SOSCDIV_DIV2_NUM           ((0x1) << SCG_SOSCDIV_DIV2_SHIFT)
1000 /* Enable FIRC DIV1 */
1001 #define SCG1_SOSCDIV_DIV1_NUM           ((0x1) << SCG_SOSCDIV_DIV1_SHIFT)
1002
1003 void scg_a7_soscdiv_init(void)
1004 {
1005         /* Wait for FIRC clock ready */
1006         while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))
1007                 ;
1008
1009         /* Configure A7 FIRC DIV1 ~ DIV3 */
1010         writel((SCG1_SOSCDIV_DIV3_NUM | SCG1_SOSCDIV_DIV2_NUM |
1011                SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv);
1012 }
1013
1014 void scg_a7_sys_clk_sel(enum scg_sys_src clk)
1015 {
1016         u32 rccr_reg_val = 0;
1017
1018         clk_debug("%s: system clock selected as %s\n", "[SCG]",
1019                   clk == SCG_SCS_SYS_OSC ? "SYS_OSC" :
1020                   clk == SCG_SCS_SLOW_IRC  ? "SLOW_IRC" :
1021                   clk == SCG_SCS_FAST_IRC  ? "FAST_IRC" :
1022                   clk == SCG_SCS_RTC_OSC   ? "RTC_OSC" :
1023                   clk == SCG_SCS_AUX_PLL   ? "AUX_PLL" :
1024                   clk == SCG_SCS_SYS_PLL   ? "SYS_PLL" :
1025                   clk == SCG_SCS_USBPHY_PLL ? "USBPHY_PLL" :
1026                   "Invalid source"
1027         );
1028
1029         rccr_reg_val = readl(&scg1_regs->rccr);
1030         rccr_reg_val &= ~SCG_CCR_SCS_MASK;
1031         rccr_reg_val |= (clk << SCG_CCR_SCS_SHIFT);
1032         writel(rccr_reg_val, &scg1_regs->rccr);
1033 }
1034
1035 void scg_a7_info(void)
1036 {
1037         debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));
1038         debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));
1039         debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));
1040         debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));
1041 }
1042
1043 void scg_a7_init_core_clk(void)
1044 {
1045         u32 val = 0;
1046
1047         /*
1048          * The normal target frequency for ULP B0 is 500Mhz,
1049          * but ROM set it to 413Mhz, need to change SPLL PFD0 FRAC
1050          */
1051         if (soc_rev() >= CHIP_REV_2_0) {
1052                 /* Switch RCCR SCG to SOSC, firstly check the SOSC is valid */
1053                 if ((readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) {
1054                         val = readl(&scg1_regs->rccr);
1055                         val &= (~SCG_CCR_SCS_MASK);
1056                         val |= ((SCG_SCS_SYS_OSC) << SCG_CCR_SCS_SHIFT);
1057                         writel(val, &scg1_regs->rccr);
1058
1059                         /* Switch the PLLS to SPLL clk */
1060                         val = readl(&scg1_regs->spllcfg);
1061                         val &= ~SCG_PLL_CFG_PLLSEL_MASK;
1062                         writel(val, &scg1_regs->spllcfg);
1063
1064                         /*
1065                          * Re-configure PFD0 to 19,
1066                          * A7 SPLL(528MHz) * 18 / 19 = 500MHz
1067                          */
1068                         scg_enable_pll_pfd(SCG_SPLL_PFD0_CLK, 19);
1069
1070                         /* Switch the PLLS to SPLL PFD0 */
1071                         val = readl(&scg1_regs->spllcfg);
1072                         val |= SCG_PLL_CFG_PLLSEL_MASK;
1073                         writel(val, &scg1_regs->spllcfg);
1074
1075                         /* Set RCCR SCG to SPLL clk out */
1076                         val = readl(&scg1_regs->rccr);
1077                         val &= (~SCG_CCR_SCS_MASK);
1078                         val |= ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT);
1079                         writel(val, &scg1_regs->rccr);
1080                 }
1081         }
1082 }