3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/bootm.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/dma.h>
19 #include <asm/mach-imx/hab.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/arch/crm_regs.h>
24 #include <imx_thermal.h>
41 #if defined(CONFIG_IMX_THERMAL)
42 static const struct imx_thermal_plat imx6_thermal_plat = {
43 .regs = (void *)ANATOP_BASE_ADDR,
48 U_BOOT_DEVICE(imx6_thermal) = {
49 .name = "imx_thermal",
50 .platdata = &imx6_thermal_plat,
54 #if defined(CONFIG_SECURE_BOOT)
55 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
63 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
64 return readl(&scu->config) & 3;
69 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
70 u32 reg = readl(&anatop->digprog_sololite);
71 u32 type = ((reg >> 16) & 0xff);
74 if (type != MXC_CPU_MX6SL) {
75 reg = readl(&anatop->digprog);
76 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
77 cfg = readl(&scu->config) & 3;
78 type = ((reg >> 16) & 0xff);
79 if (type == MXC_CPU_MX6DL) {
81 type = MXC_CPU_MX6SOLO;
84 if (type == MXC_CPU_MX6Q) {
90 major = ((reg >> 8) & 0xff);
92 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
98 reg &= 0xff; /* mx6 silicon revision */
99 return (type << 12) | (reg + (0x10 * (major + 1)));
103 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
104 * defines a 2-bit SPEED_GRADING
106 #define OCOTP_CFG3_SPEED_SHIFT 16
107 #define OCOTP_CFG3_SPEED_800MHZ 0
108 #define OCOTP_CFG3_SPEED_850MHZ 1
109 #define OCOTP_CFG3_SPEED_1GHZ 2
110 #define OCOTP_CFG3_SPEED_1P2GHZ 3
115 #define OCOTP_CFG3_SPEED_528MHZ 1
116 #define OCOTP_CFG3_SPEED_696MHZ 2
121 #define OCOTP_CFG3_SPEED_792MHZ 2
122 #define OCOTP_CFG3_SPEED_900MHZ 3
124 u32 get_cpu_speed_grade_hz(void)
126 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
127 struct fuse_bank *bank = &ocotp->bank[0];
128 struct fuse_bank0_regs *fuse =
129 (struct fuse_bank0_regs *)bank->fuse_regs;
132 val = readl(&fuse->cfg3);
133 val >>= OCOTP_CFG3_SPEED_SHIFT;
137 if (val == OCOTP_CFG3_SPEED_528MHZ)
139 else if (val == OCOTP_CFG3_SPEED_696MHZ)
146 if (val == OCOTP_CFG3_SPEED_528MHZ)
148 else if (val == OCOTP_CFG3_SPEED_792MHZ)
150 else if (val == OCOTP_CFG3_SPEED_900MHZ)
157 /* Valid for IMX6DQ */
158 case OCOTP_CFG3_SPEED_1P2GHZ:
159 if (is_mx6dq() || is_mx6dqp())
161 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
162 case OCOTP_CFG3_SPEED_1GHZ:
164 /* Valid for IMX6DQ */
165 case OCOTP_CFG3_SPEED_850MHZ:
166 if (is_mx6dq() || is_mx6dqp())
168 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
169 case OCOTP_CFG3_SPEED_800MHZ:
176 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
177 * defines a 2-bit Temperature Grade
179 * return temperature grade and min/max temperature in Celsius
181 #define OCOTP_MEM0_TEMP_SHIFT 6
183 u32 get_cpu_temp_grade(int *minc, int *maxc)
185 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
186 struct fuse_bank *bank = &ocotp->bank[1];
187 struct fuse_bank1_regs *fuse =
188 (struct fuse_bank1_regs *)bank->fuse_regs;
191 val = readl(&fuse->mem0);
192 val >>= OCOTP_MEM0_TEMP_SHIFT;
196 if (val == TEMP_AUTOMOTIVE) {
199 } else if (val == TEMP_INDUSTRIAL) {
202 } else if (val == TEMP_EXTCOMMERCIAL) {
213 #ifdef CONFIG_REVISION_TAG
214 u32 __weak get_board_rev(void)
216 u32 cpurev = get_cpu_rev();
217 u32 type = ((cpurev >> 12) & 0xff);
218 if (type == MXC_CPU_MX6SOLO)
219 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
221 if (type == MXC_CPU_MX6D)
222 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
228 static void clear_ldo_ramp(void)
230 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
233 /* ROM may modify LDO ramp up time according to fuse setting, so in
234 * order to be in the safe side we neeed to reset these settings to
235 * match the reset value: 0'b00
237 reg = readl(&anatop->ana_misc2);
238 reg &= ~(0x3f << 24);
239 writel(reg, &anatop->ana_misc2);
243 * Set the PMU_REG_CORE register
245 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
246 * Possible values are from 0.725V to 1.450V in steps of
249 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
251 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
252 u32 val, step, old, reg = readl(&anatop->reg_core);
255 /* No LDO_SOC/PU/ARM */
260 val = 0x00; /* Power gated off */
262 val = 0x1F; /* Power FET switched full on. No regulation */
264 val = (mv - 700) / 25;
282 old = (reg & (0x1F << shift)) >> shift;
283 step = abs(val - old);
287 reg = (reg & ~(0x1F << shift)) | (val << shift);
288 writel(reg, &anatop->reg_core);
291 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
299 static void set_ahb_rate(u32 val)
301 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
304 div = get_periph_clk() / val - 1;
305 reg = readl(&mxc_ccm->cbcdr);
307 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
308 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
311 static void clear_mmdc_ch_mask(void)
313 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
315 reg = readl(&mxc_ccm->ccdr);
317 /* Clear MMDC channel mask */
318 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
319 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
321 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
322 writel(reg, &mxc_ccm->ccdr);
325 #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
327 static void init_bandgap(void)
329 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
330 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
331 struct fuse_bank *bank = &ocotp->bank[1];
332 struct fuse_bank1_regs *fuse =
333 (struct fuse_bank1_regs *)bank->fuse_regs;
337 * Ensure the bandgap has stabilized.
339 while (!(readl(&anatop->ana_misc0) & 0x80))
342 * For best noise performance of the analog blocks using the
343 * outputs of the bandgap, the reftop_selfbiasoff bit should
346 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
348 * On i.MX6ULL,we need to set VBGADJ bits according to the
349 * REFTOP_TRIM[3:0] in fuse table
350 * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
351 * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
352 * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
353 * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
354 * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
355 * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
356 * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
357 * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
360 val = readl(&fuse->mem0);
361 val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
364 writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
365 &anatop->ana_misc0_set);
369 int arch_cpu_init(void)
371 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
375 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
376 clear_mmdc_ch_mask();
379 * Disable self-bias circuit in the analog bandap.
380 * The self-bias circuit is used by the bandgap during startup.
381 * This bit should be set after the bandgap has initialized.
385 if (!is_mx6ul() && !is_mx6ull()) {
387 * When low freq boot is enabled, ROM will not set AHB
388 * freq, so we need to ensure AHB freq is 132MHz in such
391 * To i.MX6UL, when power up, default ARM core and
392 * AHB rate is 396M and 132M.
394 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
395 set_ahb_rate(132000000);
399 if (is_soc_rev(CHIP_REV_1_0) == 0) {
401 * According to the design team's requirement on
402 * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
403 * as open drain 100K (0x0000b8a0).
404 * Only exists on TO1.0
406 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
409 * From TO1.1, SNVS adds internal pull up control
410 * for POR_B, the register filed is GPBIT[1:0],
411 * after system boot up, it can be set to 2b'01
412 * to disable internal pull up.It can save about
413 * 30uA power in SNVS mode.
415 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
417 MX6UL_SNVS_LP_BASE_ADDR + 0x10);
423 * GPBIT[1:0] is suggested to set to 2'b11:
424 * 2'b00 : always PUP100K
425 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
426 * 2'b10 : always disable PUP100K
427 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
428 * register offset is different from i.MX6UL, since
429 * i.MX6UL is fixed by ECO.
431 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
432 0x3, MX6UL_SNVS_LP_BASE_ADDR);
435 /* Set perclk to source from OSC 24MHz */
437 setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
439 imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
442 setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
449 #ifdef CONFIG_ENV_IS_IN_MMC
450 __weak int board_mmc_get_env_dev(int devno)
452 return CONFIG_SYS_MMC_ENV_DEV;
455 static int mmc_get_boot_dev(void)
457 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
458 u32 soc_sbmr = readl(&src_regs->sbmr1);
464 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
465 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
466 * i.MX6SL/SX/UL has same layout.
468 bootsel = (soc_sbmr & 0x000000FF) >> 6;
470 /* No boot from sd/mmc */
474 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
475 devno = (soc_sbmr & 0x00001800) >> 11;
480 int mmc_get_env_dev(void)
482 int devno = mmc_get_boot_dev();
484 /* If not boot from sd/mmc, use default value */
486 return CONFIG_SYS_MMC_ENV_DEV;
488 return board_mmc_get_env_dev(devno);
491 #ifdef CONFIG_SYS_MMC_ENV_PART
492 __weak int board_mmc_get_env_part(int devno)
494 return CONFIG_SYS_MMC_ENV_PART;
497 uint mmc_get_env_part(struct mmc *mmc)
499 int devno = mmc_get_boot_dev();
501 /* If not boot from sd/mmc, use default value */
503 return CONFIG_SYS_MMC_ENV_PART;
505 return board_mmc_get_env_part(devno);
510 int board_postclk_init(void)
512 /* NO LDO SOC on i.MX6SLL */
516 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
521 #ifndef CONFIG_SPL_BUILD
523 * cfg_val will be used for
524 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
525 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
526 * instead of SBMR1 to determine the boot device.
528 const struct boot_mode soc_boot_modes[] = {
529 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
530 /* reserved value should start rom usb */
531 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
532 {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
534 {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
536 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
537 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
538 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
539 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
540 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
541 /* 4 bit bus width */
542 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
543 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
544 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
545 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
550 void reset_misc(void)
552 #ifdef CONFIG_VIDEO_MXS
559 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
560 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
563 u32 reg, periph1, periph2;
565 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
568 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
569 * to make sure PFD is working right, otherwise, PFDs may
570 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
571 * workaround in ROM code, as bus clock need it
574 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
575 ANATOP_PFD_CLKGATE_MASK(1) |
576 ANATOP_PFD_CLKGATE_MASK(2) |
577 ANATOP_PFD_CLKGATE_MASK(3);
578 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
579 ANATOP_PFD_CLKGATE_MASK(3);
581 reg = readl(&ccm->cbcmr);
582 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
583 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
584 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
585 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
587 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
588 if ((periph2 != 0x2) && (periph1 != 0x2))
589 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
591 if ((periph2 != 0x1) && (periph1 != 0x1) &&
592 (periph2 != 0x3) && (periph1 != 0x3))
593 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
595 writel(mask480, &anatop->pfd_480_set);
596 writel(mask528, &anatop->pfd_528_set);
597 writel(mask480, &anatop->pfd_480_clr);
598 writel(mask528, &anatop->pfd_528_clr);
601 #ifdef CONFIG_IMX_HDMI
602 void imx_enable_hdmi_phy(void)
604 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
606 reg = readb(&hdmi->phy_conf0);
607 reg |= HDMI_PHY_CONF0_PDZ_MASK;
608 writeb(reg, &hdmi->phy_conf0);
610 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
611 writeb(reg, &hdmi->phy_conf0);
613 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
614 writeb(reg, &hdmi->phy_conf0);
615 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
618 void imx_setup_hdmi(void)
620 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
621 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
625 /* Turn on HDMI PHY clock */
626 reg = readl(&mxc_ccm->CCGR2);
627 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
628 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
629 writel(reg, &mxc_ccm->CCGR2);
630 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
631 reg = readl(&mxc_ccm->chsccdr);
632 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
633 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
634 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
635 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
636 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
637 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
638 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
639 writel(reg, &mxc_ccm->chsccdr);
641 /* Clear the overflow condition */
642 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
643 /* TMDS software reset */
644 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
645 val = readb(&hdmi->fc_invidconf);
646 /* Need minimum 3 times to write to clear the register */
647 for (count = 0 ; count < 5 ; count++)
648 writeb(val, &hdmi->fc_invidconf);
655 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
657 /* enable AXI cache for VDOA/VPU/IPU */
658 writel(0xF00000CF, &iomux->gpr[4]);
660 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
661 writel(0x77177717, &iomux->gpr[6]);
662 writel(0x77177717, &iomux->gpr[7]);
664 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
665 writel(0x007F007F, &iomux->gpr[6]);
666 writel(0x007F007F, &iomux->gpr[7]);