1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Stefan Roese <sr@denx.de>
9 #include <asm/arch/sys_proto.h>
10 #include <linux/errno.h>
12 #include <asm/mach-imx/regs-common.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 /* 1 second delay should be plenty of time for block reset. */
17 #define RESET_MAX_TIMEOUT 1000000
19 #define MXS_BLOCK_SFTRST (1 << 31)
20 #define MXS_BLOCK_CLKGATE (1 << 30)
22 int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
26 if ((readl(®->reg) & mask) == mask)
34 int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
38 if ((readl(®->reg) & mask) == 0)
46 int mxs_reset_block(struct mxs_register_32 *reg)
49 writel(MXS_BLOCK_SFTRST, ®->reg_clr);
51 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
55 writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
58 writel(MXS_BLOCK_SFTRST, ®->reg_set);
60 /* Wait for CLKGATE being set */
61 if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
65 writel(MXS_BLOCK_SFTRST, ®->reg_clr);
67 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
71 writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
73 if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
79 static ulong get_sp(void)
83 asm("mov %0, sp" : "=r"(ret) : );
87 void board_lmb_reserve(struct lmb *lmb)
93 debug("## Current stack ends at 0x%08lx ", sp);
95 /* adjust sp by 16K to be safe */
97 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
98 if (sp < gd->bd->bi_dram[bank].start)
100 bank_end = gd->bd->bi_dram[bank].start +
101 gd->bd->bi_dram[bank].size;
104 lmb_reserve(lmb, sp, bank_end - sp);