arch/arm/mach-imx/imx8m/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/mach-imx/hab.h>
  14 #include <asm/mach-imx/boot_mode.h>
  15 #include <asm/mach-imx/syscounter.h>
  16 #include <asm/armv8/mmu.h>
  17 #include <errno.h>
  18 #include <fdt_support.h>
  19 #include <fsl_wdog.h>
  20 #include <imx_sip.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #if defined(CONFIG_SECURE_BOOT)
  25 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  26         .bank = 1,
  27         .word = 3,
  28 };
  29 #endif
  30
  31 int timer_init(void)
  32 {
  33 #ifdef CONFIG_SPL_BUILD
  34         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  35         unsigned long freq = readl(&sctr->cntfid0);
  36
  37         /* Update with accurate clock frequency */
  38         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  39
  40         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  41                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  42 #endif
  43
  44         gd->arch.tbl = 0;
  45         gd->arch.tbu = 0;
  46
  47         return 0;
  48 }
  49
  50 void enable_tzc380(void)
  51 {
  52         struct iomuxc_gpr_base_regs *gpr =
  53                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  54
  55         /* Enable TZASC and lock setting */
  56         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  57         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  58         if (IS_ENABLED(CONFIG_IMX8MM))
  59                 setbits_le32(&gpr->gpr[10], BIT(1));
  60 }
  61
  62 void set_wdog_reset(struct wdog_regs *wdog)
  63 {
  64         /*
  65          * Output WDOG_B signal to reset external pmic or POR_B decided by
  66          * the board design. Without external reset, the peripherals/DDR/
  67          * PMIC are not reset, that may cause system working abnormal.
  68          * WDZST bit is write-once only bit. Align this bit in kernel,
  69          * otherwise kernel code will have no chance to set this bit.
  70          */
  71         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  72 }
  73
  74 static struct mm_region imx8m_mem_map[] = {
  75         {
  76                 /* ROM */
  77                 .virt = 0x0UL,
  78                 .phys = 0x0UL,
  79                 .size = 0x100000UL,
  80                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  81                          PTE_BLOCK_OUTER_SHARE
  82         }, {
  83                 /* CAAM */
  84                 .virt = 0x100000UL,
  85                 .phys = 0x100000UL,
  86                 .size = 0x8000UL,
  87                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  88                          PTE_BLOCK_NON_SHARE |
  89                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  90         }, {
  91                 /* TCM */
  92                 .virt = 0x7C0000UL,
  93                 .phys = 0x7C0000UL,
  94                 .size = 0x80000UL,
  95                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  96                          PTE_BLOCK_NON_SHARE |
  97                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  98         }, {
  99                 /* OCRAM */
 100                 .virt = 0x900000UL,
 101                 .phys = 0x900000UL,
 102                 .size = 0x200000UL,
 103                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 104                          PTE_BLOCK_OUTER_SHARE
 105         }, {
 106                 /* AIPS */
 107                 .virt = 0xB00000UL,
 108                 .phys = 0xB00000UL,
 109                 .size = 0x3f500000UL,
 110                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 111                          PTE_BLOCK_NON_SHARE |
 112                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 113         }, {
 114                 /* DRAM1 */
 115                 .virt = 0x40000000UL,
 116                 .phys = 0x40000000UL,
 117                 .size = PHYS_SDRAM_SIZE,
 118                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 119                          PTE_BLOCK_OUTER_SHARE
 120 #ifdef PHYS_SDRAM_2_SIZE
 121         }, {
 122                 /* DRAM2 */
 123                 .virt = 0x100000000UL,
 124                 .phys = 0x100000000UL,
 125                 .size = PHYS_SDRAM_2_SIZE,
 126                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 127                          PTE_BLOCK_OUTER_SHARE
 128 #endif
 129         }, {
 130                 /* List terminator */
 131                 0,
 132         }
 133 };
 134
 135 struct mm_region *mem_map = imx8m_mem_map;
 136
 137 void enable_caches(void)
 138 {
 139         /*
 140          * If OPTEE runs, remove OPTEE memory from MMU table to
 141          * avoid speculative prefetch. OPTEE runs at the top of
 142          * the first memory bank
 143          */
 144         if (rom_pointer[1])
 145                 imx8m_mem_map[5].size -= rom_pointer[1];
 146
 147         icache_enable();
 148         dcache_enable();
 149 }
 150
 151 static u32 get_cpu_variant_type(u32 type)
 152 {
 153         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 154         struct fuse_bank *bank = &ocotp->bank[1];
 155         struct fuse_bank1_regs *fuse =
 156                 (struct fuse_bank1_regs *)bank->fuse_regs;
 157
 158         u32 value = readl(&fuse->tester4);
 159
 160         if (type == MXC_CPU_IMX8MM) {
 161                 switch (value & 0x3) {
 162                 case 2:
 163                         if (value & 0x1c0000)
 164                                 return MXC_CPU_IMX8MMDL;
 165                         else
 166                                 return MXC_CPU_IMX8MMD;
 167                 case 3:
 168                         if (value & 0x1c0000)
 169                                 return MXC_CPU_IMX8MMSL;
 170                         else
 171                                 return MXC_CPU_IMX8MMS;
 172                 default:
 173                         if (value & 0x1c0000)
 174                                 return MXC_CPU_IMX8MML;
 175                         break;
 176                 }
 177         }
 178
 179         return type;
 180 }
 181
 182 u32 get_cpu_rev(void)
 183 {
 184         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 185         u32 reg = readl(&ana_pll->digprog);
 186         u32 type = (reg >> 16) & 0xff;
 187         u32 major_low = (reg >> 8) & 0xff;
 188         u32 rom_version;
 189
 190         reg &= 0xff;
 191
 192         /* i.MX8MM */
 193         if (major_low == 0x41) {
 194                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 195         } else {
 196                 if (reg == CHIP_REV_1_0) {
 197                         /*
 198                          * For B0 chip, the DIGPROG is not updated, still TO1.0.
 199                          * we have to check ROM version further
 200                          */
 201                         rom_version = readl((void __iomem *)ROM_VERSION_A0);
 202                         if (rom_version != CHIP_REV_1_0) {
 203                                 rom_version = readl((void __iomem *)ROM_VERSION_B0);
 204                                 if (rom_version >= CHIP_REV_2_0)
 205                                         reg = CHIP_REV_2_0;
 206                         }
 207                 }
 208         }
 209
 210         return (type << 12) | reg;
 211 }
 212
 213 static void imx_set_wdog_powerdown(bool enable)
 214 {
 215         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 216         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 217         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 218
 219         /* Write to the PDE (Power Down Enable) bit */
 220         writew(enable, &wdog1->wmcr);
 221         writew(enable, &wdog2->wmcr);
 222         writew(enable, &wdog3->wmcr);
 223 }
 224
 225 int arch_cpu_init(void)
 226 {
 227         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 228         /*
 229          * Init timer at very early state, because sscg pll setting
 230          * will use it
 231          */
 232         timer_init();
 233
 234         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 235                 clock_init();
 236                 imx_set_wdog_powerdown(false);
 237         }
 238
 239         if (is_imx8mq()) {
 240                 clock_enable(CCGR_OCOTP, 1);
 241                 if (readl(&ocotp->ctrl) & 0x200)
 242                         writel(0x200, &ocotp->ctrl_clr);
 243         }
 244
 245         return 0;
 246 }
 247
 248 bool is_usb_boot(void)
 249 {
 250         return get_boot_device() == USB_BOOT;
 251 }
 252
 253 #ifdef CONFIG_OF_SYSTEM_SETUP
 254 int ft_system_setup(void *blob, bd_t *bd)
 255 {
 256         int i = 0;
 257         int rc;
 258         int nodeoff;
 259
 260         /* Disable the CPU idle for A0 chip since the HW does not support it */
 261         if (is_soc_rev(CHIP_REV_1_0)) {
 262                 static const char * const nodes_path[] = {
 263                         "/cpus/cpu@0",
 264                         "/cpus/cpu@1",
 265                         "/cpus/cpu@2",
 266                         "/cpus/cpu@3",
 267                 };
 268
 269                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
 270                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
 271                         if (nodeoff < 0)
 272                                 continue; /* Not found, skip it */
 273
 274                         printf("Found %s node\n", nodes_path[i]);
 275
 276                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
 277                         if (rc) {
 278                                 printf("Unable to update property %s:%s, err=%s\n",
 279                                        nodes_path[i], "status", fdt_strerror(rc));
 280                                 return rc;
 281                         }
 282
 283                         printf("Remove %s:%s\n", nodes_path[i],
 284                                "cpu-idle-states");
 285                 }
 286         }
 287
 288         return 0;
 289 }
 290 #endif
 291
 292 void reset_cpu(ulong addr)
 293 {
 294         struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 295
 296         /* Clear WDA to trigger WDOG_B immediately */
 297         writew((WCR_WDE | WCR_SRS), &wdog->wcr);
 298
 299         while (1) {
 300                 /*
 301                  * spin for .5 seconds before reset
 302                  */
 303         }
 304 }