arch/arm/mach-imx/imx8m/clock_slice.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/io.h>
  12 #include <errno.h>
  13
  14 static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
  15
  16 #ifdef CONFIG_IMX8MQ
  17 static struct clk_root_map root_array[] = {
  18         {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
  19          {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  20           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  21           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
  22         },
  23         {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
  24          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
  25           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  26           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  27         },
  28         {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
  29          {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  30           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  31           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
  32         },
  33         {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
  34          {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  35           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  36           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  37         },
  38         {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
  39          {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  40           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  41           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  42         },
  43         {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
  44          {OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
  45           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
  46           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
  47         },
  48         {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
  49          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  50           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  51           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  52         },
  53         {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
  54          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  55           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
  56           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
  57         },
  58         {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
  59          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
  60           AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  61           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
  62         },
  63         {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
  64          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  65           SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
  66           EXT_CLK_1, EXT_CLK_4}
  67         },
  68         {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
  69          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  70           SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
  71           EXT_CLK_1, EXT_CLK_3}
  72         },
  73         {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
  74          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
  75           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  76           EXT_CLK_2, EXT_CLK_3}
  77         },
  78         {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
  79          {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  80           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  81           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  82         },
  83         {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
  84          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  85           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  86           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  87         },
  88         {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
  89          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  90           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  91           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  92         },
  93         {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
  94          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
  95           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
  96           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  97         },
  98         {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
  99          {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
 100           SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
 101           SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 102         },
 103         {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
 104          {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
 105           SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
 106           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 107         },
 108         {IPG_CLK_ROOT, IPG_CLOCK_SLICE, 0,
 109          {}
 110         },
 111         {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
 112          {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
 113           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
 114           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 115         },
 116         {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
 117          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_40M_CLK,
 118           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 119           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL1_CLK },
 120         },
 121         {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
 122          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
 123           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_250M_CLK,
 124           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
 125         },
 126         {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
 127          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 128           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 129           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 130         },
 131         {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
 132          {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 133           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
 134           SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
 135         },
 136         {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
 137          {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 138           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
 139           SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
 140         },
 141         {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
 142          {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 143           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
 144           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
 145         },
 146         {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
 147          {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 148           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
 149           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
 150         },
 151         {PCIE1_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
 152          {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
 153           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 154           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
 155         },
 156         {PCIE1_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
 157          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
 158           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
 159           SYSTEM_PLL1_400M_CLK}
 160         },
 161         {PCIE1_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
 162          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
 163           SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 164           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
 165         },
 166         {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
 167          {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
 168           AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
 169           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
 170         },
 171         {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
 172          {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
 173           AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
 174           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
 175         },
 176         {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
 177          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 178           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 179           OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
 180         },
 181         {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
 182          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 183           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 184           OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
 185         },
 186         {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
 187          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 188           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 189           OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
 190         },
 191         {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
 192          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 193           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 194           OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
 195         },
 196         {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
 197          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 198           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 199           OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
 200         },
 201         {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
 202          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 203           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 204           OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
 205         },
 206         {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
 207          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 208           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 209           OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
 210         },
 211         {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
 212          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 213           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 214           OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
 215         },
 216         {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
 217          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
 218           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 219           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
 220         },
 221         {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
 222          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
 223           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
 224           VIDEO_PLL_CLK}
 225         },
 226         {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
 227          {OSC_25M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
 228           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
 229           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 230         },
 231         {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
 232          {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
 233           SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
 234           SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
 235         },
 236         {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
 237          {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 238           SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
 239           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
 240         },
 241         {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
 242          {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 243           SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
 244           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
 245         },
 246         {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
 247          {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 248           SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
 249           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
 250         },
 251         {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
 252          {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 253           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 254           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 255         },
 256         {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
 257          {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 258           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 259           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 260         },
 261         {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
 262          {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 263           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 264           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 265         },
 266         {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
 267          {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 268           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 269           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 270         },
 271         {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
 272          {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 273           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 274           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 275         },
 276         {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
 277          {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 278           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 279           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 280         },
 281         {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
 282          {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 283           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 284           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 285         },
 286         {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
 287          {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 288           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 289           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 290         },
 291         {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
 292          {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
 293           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
 294           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 295         },
 296         {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
 297          {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
 298           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
 299           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 300         },
 301         {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
 302          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 303           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
 304           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 305         },
 306         {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
 307          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 308           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 309           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 310         },
 311         {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
 312          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 313           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 314           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 315         },
 316         {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
 317          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 318           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 319           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 320         },
 321         {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
 322          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 323           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 324           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 325         },
 326         {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
 327          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 328           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 329           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 330         },
 331         {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
 332          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 333           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 334           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 335         },
 336         {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
 337          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 338           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 339           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
 340         },
 341         {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
 342          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 343           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 344           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
 345         },
 346         {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
 347          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 348           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 349           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
 350         },
 351         {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
 352          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 353           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 354           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
 355         },
 356         {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
 357          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 358           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 359           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
 360         },
 361         {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
 362          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 363           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 364           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
 365         },
 366         {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
 367          {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
 368           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
 369           SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
 370         },
 371         {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
 372          {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
 373           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
 374           SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
 375         },
 376         {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
 377          {OSC_25M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
 378           SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
 379           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
 380         },
 381         {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
 382          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK,
 383           SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
 384           SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
 385         },
 386         {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
 387          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
 388           SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
 389           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
 390         },
 391         {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
 392          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
 393           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 394           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 395         },
 396         {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
 397          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
 398           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 399           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 400         },
 401         {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
 402          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
 403           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 404           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 405         },
 406         {OLD_MIPI_DSI_ESC_CLK_ROOT, IP_CLOCK_SLICE, 57,
 407          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 408           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 409           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
 410         },
 411         {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
 412          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
 413           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 414           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 415         },
 416         {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
 417          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
 418           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 419           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 420         },
 421         {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
 422          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 423           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 424           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
 425         },
 426         {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
 427          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
 428           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 429           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 430         },
 431         {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
 432          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
 433           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 434           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 435         },
 436         {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
 437          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 438           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 439           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
 440         },
 441         {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
 442          {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
 443           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 444           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
 445         },
 446         {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
 447          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
 448           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
 449           EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
 450         },
 451         {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
 452          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
 453           SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
 454           SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
 455         },
 456         {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
 457          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 458           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 459           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 460         },
 461         {OLD_MIPI_DSI_ESC_RX_ROOT, IP_CLOCK_SLICE, 68,
 462          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 463           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 464           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
 465         },
 466         {DISPLAY_HDMI_CLK_ROOT, IP_CLOCK_SLICE, 69,
 467          {OSC_25M_CLK, SYSTEM_PLL1_200M_CLK, SYSTEM_PLL2_200M_CLK,
 468           VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 469           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
 470         },
 471         {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
 472          {DRAM_PLL1_CLK}
 473         },
 474         {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
 475          {ARM_A53_ALT_CLK, ARM_PLL_CLK}
 476         },
 477 };
 478 #elif defined(CONFIG_IMX8MM)
 479 static struct clk_root_map root_array[] = {
 480         {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
 481          {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
 482           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
 483           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
 484         },
 485         {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
 486          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
 487           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 488           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
 489         },
 490         {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
 491          {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
 492           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
 493           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
 494         },
 495         {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
 496          {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 497           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 498           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 499         },
 500         {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
 501          {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 502           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 503           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 504         },
 505         {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
 506          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
 507           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
 508           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
 509         },
 510         {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
 511          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 512           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
 513           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
 514         },
 515         {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
 516          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 517           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
 518           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
 519         },
 520         {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
 521          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
 522           AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 523           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
 524         },
 525         {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
 526          {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
 527           SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
 528           EXT_CLK_1, EXT_CLK_4}
 529         },
 530         {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
 531          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
 532           SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
 533           EXT_CLK_1, EXT_CLK_3}
 534         },
 535         {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
 536          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
 537           SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 538           EXT_CLK_2, EXT_CLK_3}
 539         },
 540         {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
 541          {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
 542           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
 543           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 544         },
 545         {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
 546          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
 547           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 548           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 549         },
 550         {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
 551          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
 552           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 553           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 554         },
 555         {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
 556          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
 557           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
 558           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 559         },
 560         {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
 561          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
 562           SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
 563           SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 564         },
 565         {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
 566          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
 567           SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
 568           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 569         },
 570         {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
 571          {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
 572           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
 573           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 574         },
 575         {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
 576          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 577           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 578           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
 579         },
 580         {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
 581          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
 582           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
 583           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
 584         },
 585         {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
 586          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 587           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 588           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 589         },
 590         {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
 591          {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 592           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
 593           SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
 594         },
 595         {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
 596          {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 597           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
 598           SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
 599         },
 600         {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
 601          {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
 602           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
 603           VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
 604         },
 605         {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
 606          {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
 607           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
 608           VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
 609         },
 610         {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
 611          {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
 612           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 613           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
 614         },
 615         {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
 616          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
 617           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
 618           SYSTEM_PLL1_400M_CLK}
 619         },
 620         {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
 621          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
 622           SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 623           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
 624         },
 625         {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
 626          {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
 627           AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
 628           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
 629         },
 630         {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
 631          {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
 632           AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
 633           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
 634         },
 635         {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
 636          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 637           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 638           OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
 639         },
 640         {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
 641          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 642           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 643           OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
 644         },
 645         {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
 646          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 647           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 648           OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
 649         },
 650         {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
 651          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 652           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 653           OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
 654         },
 655         {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
 656          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 657           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 658           OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
 659         },
 660         {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
 661          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 662           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 663           OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
 664         },
 665         {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
 666          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 667           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 668           OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
 669         },
 670         {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
 671          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 672           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 673           OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
 674         },
 675         {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
 676          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
 677           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 678           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
 679         },
 680         {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
 681          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
 682           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
 683           VIDEO_PLL_CLK}
 684         },
 685         {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
 686          {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
 687           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
 688           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 689         },
 690         {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
 691          {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
 692           SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
 693           SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
 694         },
 695         {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
 696          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
 697           SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
 698           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
 699         },
 700         {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
 701          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 702           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
 703           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
 704         },
 705         {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
 706          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 707           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
 708           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
 709         },
 710         {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
 711          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 712           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 713           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 714         },
 715         {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
 716          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 717           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 718           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 719         },
 720         {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
 721          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 722           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 723           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 724         },
 725         {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
 726          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 727           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 728           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 729         },
 730         {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
 731          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 732           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 733           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 734         },
 735         {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
 736          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 737           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 738           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 739         },
 740         {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
 741          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 742           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 743           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 744         },
 745         {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
 746          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 747           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 748           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 749         },
 750         {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
 751          {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
 752           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
 753           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 754         },
 755         {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
 756          {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
 757           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
 758           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 759         },
 760         {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
 761          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 762           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
 763           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 764         },
 765         {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
 766          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 767           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 768           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 769         },
 770         {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
 771          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 772           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 773           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 774         },
 775         {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
 776          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 777           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 778           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 779         },
 780         {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
 781          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 782           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 783           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 784         },
 785         {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
 786          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 787           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
 788           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 789         },
 790         {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
 791          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 792           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
 793           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 794         },
 795         {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
 796          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 797           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 798           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
 799         },
 800         {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
 801          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 802           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 803           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
 804         },
 805         {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
 806          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 807           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 808           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
 809         },
 810         {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
 811          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 812           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 813           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
 814         },
 815         {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
 816          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 817           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 818           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
 819         },
 820         {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
 821          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 822           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 823           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
 824         },
 825         {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
 826          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
 827           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
 828           SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
 829         },
 830         {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
 831          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
 832           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
 833           SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
 834         },
 835         {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
 836          {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
 837           SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
 838           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
 839         },
 840         {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
 841          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
 842           SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
 843           SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
 844         },
 845         {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
 846          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
 847           SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
 848           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
 849         },
 850         {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
 851          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
 852           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 853           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 854         },
 855         {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
 856          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
 857           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 858           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 859         },
 860         {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
 861          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
 862           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 863           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 864         },
 865         {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
 866          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 867           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
 868           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
 869         },
 870         {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
 871          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
 872           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 873           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 874         },
 875         {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
 876          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
 877           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 878           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 879         },
 880         {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
 881          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 882           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 883           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
 884         },
 885         {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
 886          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
 887           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 888           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 889         },
 890         {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
 891          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
 892           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 893           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 894         },
 895         {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
 896          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 897           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 898           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
 899         },
 900         {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
 901          {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
 902           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 903           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
 904         },
 905         {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
 906          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
 907           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
 908           EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
 909         },
 910         {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
 911          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
 912           SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
 913           SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
 914         },
 915         {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
 916          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 917           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 918           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 919         },
 920         {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
 921          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
 922           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 923           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
 924         },
 925         {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
 926          {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 927           SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
 928           SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
 929         },
 930         {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
 931          {DRAM_PLL1_CLK}
 932         },
 933         {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
 934          {ARM_A53_ALT_CLK, ARM_PLL_CLK}
 935         },
 936 };
 937 #elif defined(CONFIG_IMX8MN)
 938 static struct clk_root_map root_array[] = {
 939         {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
 940          {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
 941           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
 942           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
 943         },
 944         {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
 945          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
 946           VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 947           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
 948         },
 949         {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
 950          {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 951           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 952           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 953         },
 954         {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
 955          {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 956           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 957           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 958         },
 959         {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
 960          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
 961           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
 962           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
 963         },
 964         {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
 965          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 966           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
 967           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
 968         },
 969         {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
 970          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 971           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
 972           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
 973         },
 974         {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
 975          {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
 976           SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
 977           EXT_CLK_1, EXT_CLK_4}
 978         },
 979         {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
 980          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
 981           SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
 982           EXT_CLK_1, EXT_CLK_3}
 983         },
 984         {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
 985          {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
 986           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
 987           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 988         },
 989         {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
 990          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
 991           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 992           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 993         },
 994         {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
 995          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
 996           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 997           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 998         },
 999         {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
1000          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
1001           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
1002           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1003         },
1004         {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
1005          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
1006           SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
1007           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
1008         },
1009         {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
1010          {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
1011           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
1012           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
1013         },
1014         {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
1015          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
1016           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
1017           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
1018         },
1019         {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
1020          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1021           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1022           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1023         },
1024         {DISPLAY_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
1025          {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
1026           AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
1027           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
1028         },
1029         {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
1030          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1031           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1032           OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
1033         },
1034         {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
1035          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1036           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1037           OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
1038         },
1039         {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
1040          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1041           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1042           OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
1043         },
1044         {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
1045          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1046           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1047           OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
1048         },
1049         {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
1050          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1051           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1052           OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
1053         },
1054         {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
1055          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
1056           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1057           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
1058         },
1059         {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
1060          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
1061           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
1062           VIDEO_PLL_CLK}
1063         },
1064         {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
1065          {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
1066           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
1067           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1068         },
1069         {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
1070          {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
1071           SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
1072           SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
1073         },
1074         {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
1075          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
1076           SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
1077           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
1078         },
1079         {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
1080          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1081           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1082           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1083         },
1084         {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
1085          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1086           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1087           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1088         },
1089         {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
1090          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1091           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1092           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1093         },
1094         {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
1095          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1096           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1097           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1098         },
1099         {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
1100          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1101           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1102           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1103         },
1104         {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
1105          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1106           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1107           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1108         },
1109         {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
1110          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1111           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1112           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1113         },
1114         {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
1115          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1116           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1117           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1118         },
1119         {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
1120          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1121           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1122           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1123         },
1124         {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
1125          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1126           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1127           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1128         },
1129         {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
1130          {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
1131           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
1132           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1133         },
1134         {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
1135          {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
1136           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
1137           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1138         },
1139         {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
1140          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1141           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
1142           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1143         },
1144         {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
1145          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1146           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1147           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1148         },
1149         {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
1150          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1151           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1152           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1153         },
1154         {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
1155          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1156           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
1157           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1158         },
1159         {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
1160          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1161           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
1162           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1163         },
1164         {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
1165          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1166           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
1167           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1168         },
1169         {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
1170          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1171           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
1172           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1173         },
1174         {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
1175          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1176           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1177           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
1178         },
1179         {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
1180          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1181           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1182           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
1183         },
1184         {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
1185          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1186           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1187           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
1188         },
1189         {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
1190          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1191           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1192           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
1193         },
1194         {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
1195          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1196           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1197           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
1198         },
1199         {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
1200          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1201           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1202           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
1203         },
1204         {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
1205          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
1206           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
1207           SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
1208         },
1209         {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
1210          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
1211           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
1212           SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
1213         },
1214         {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
1215          {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
1216           SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
1217           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
1218         },
1219         {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
1220          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
1221           SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
1222           SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
1223         },
1224         {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
1225          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
1226           SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
1227           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
1228         },
1229         {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
1230          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
1231           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1232           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1233         },
1234         {DISPLAY_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
1235          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
1236           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1237           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1238         },
1239         {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
1240          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
1241           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1242           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1243         },
1244         {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
1245          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1246           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1247           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1248         },
1249         {DISPLAY_CAMERA_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 58,
1250          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
1251           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1252           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1253         },
1254         {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
1255          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
1256           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1257           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1258         },
1259         {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
1260          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
1261           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1262           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1263         },
1264         {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
1265          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
1266           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1267           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
1268         },
1269         {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
1270          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1271           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1272           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1273         },
1274         {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
1275          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
1276           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1277           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
1278         },
1279         {SAI7_CLK_ROOT, IP_CLOCK_SLICE, 70,
1280          {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1281           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1282           OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
1283         },
1284         {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
1285          {DRAM_PLL1_CLK}
1286         },
1287         {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
1288          {ARM_A53_ALT_CLK, ARM_PLL_CLK}
1289         },
1290 };
1291 #elif defined(CONFIG_IMX8MP)
1292 static struct clk_root_map root_array[] = {
1293         {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
1294          {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
1295           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
1296           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
1297         },
1298         {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
1299          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
1300           VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
1301           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
1302         },
1303         {ML_CLK_ROOT, CORE_CLOCK_SLICE, 2,
1304          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
1305           VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
1306           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
1307         },
1308         {HSIO_AXI_CLK_ROOT, CORE_CLOCK_SLICE, 7,
1309          {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
1310           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, EXT_CLK_2,
1311           EXT_CLK_4, AUDIO_PLL2_CLK}
1312         },
1313         {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
1314          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
1315           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK,
1316           VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
1317         },
1318         {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
1319          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
1320           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK,
1321           VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
1322         },
1323         {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
1324          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
1325           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
1326           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
1327         },
1328         {MEDIA_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
1329          {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
1330           SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
1331           AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
1332         },
1333         {MEDIA_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
1334          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
1335           SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
1336           AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
1337         },
1338         {HDMI_APB_CLK_ROOT, BUS_CLOCK_SLICE, 6,
1339          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
1340           SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
1341           AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
1342         },
1343         {HDMI_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 7,
1344          {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
1345           SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
1346           AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
1347         },
1348         {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
1349          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
1350           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
1351           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1352         },
1353         {NOC_IO_CLK_ROOT, BUS_CLOCK_SLICE, 11,
1354          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
1355           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
1356           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1357         },
1358         {ML_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 12,
1359          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
1360           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
1361           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1362         },
1363         {ML_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 13,
1364          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
1365           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
1366           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1367         },
1368         {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
1369          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
1370           SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
1371           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
1372         },
1373         {MEDIA_DISP2_CLK_ROOT, AHB_CLOCK_SLICE, 3,
1374          {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
1375           AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
1376           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
1377         },
1378         {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
1379          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
1380           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
1381           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
1382         },
1383         {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
1384          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1385           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1386           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1387         },
1388         {I2C5_CLK_ROOT, IP_CLOCK_SLICE, 9,
1389          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1390           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
1391           SYSTEM_PLL1_133M_CLK}
1392         },
1393         {I2C6_CLK_ROOT, IP_CLOCK_SLICE, 10,
1394          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1395           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
1396           SYSTEM_PLL1_133M_CLK}
1397         },
1398         {ENET_QOS_CLK_ROOT, IP_CLOCK_SLICE, 17,
1399          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
1400           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1401           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
1402         },
1403         {ENET_QOS_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 18,
1404          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1,
1405           EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK}
1406         },
1407         {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
1408          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
1409           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1410           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
1411         },
1412         {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
1413          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1,
1414           EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK}
1415         },
1416         {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
1417          {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
1418           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
1419           VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1420         },
1421         {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
1422          {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
1423           SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
1424           SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
1425         },
1426         {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
1427          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
1428           SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
1429           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
1430         },
1431         {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
1432          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1433           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1434           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1435         },
1436         {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
1437          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1438           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1439           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1440         },
1441         {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
1442          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1443           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1444           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1445         },
1446         {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
1447          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1448           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1449           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1450         },
1451         {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
1452          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1453           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1454           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1455         },
1456         {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
1457          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1458           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1459           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1460         },
1461         {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
1462          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1463           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1464           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1465         },
1466         {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
1467          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1468           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1469           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1470         },
1471         {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
1472          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1473           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1474           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1475         },
1476         {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
1477          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1478           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1479           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1480         },
1481         {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
1482          {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
1483           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
1484           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1485         },
1486         {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
1487          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1488           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
1489           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1490         },
1491         {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
1492          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1493           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1494           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1495         },
1496         {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
1497          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1498           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1499           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1500         },
1501         {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
1502          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1503           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
1504           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1505         },
1506         {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
1507          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1508           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
1509           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1510         },
1511         {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
1512          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1513           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
1514           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1515         },
1516         {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
1517          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1518           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
1519           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1520         },
1521         {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
1522          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1523           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1524           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
1525         },
1526         {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
1527          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1528           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1529           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
1530         },
1531         {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
1532          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1533           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1534           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
1535         },
1536         {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
1537          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1538           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1539           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
1540         },
1541         {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
1542          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1543           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1544           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
1545         },
1546         {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
1547          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1548           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1549           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
1550         },
1551         {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
1552          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
1553           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
1554           SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
1555         },
1556         {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
1557          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
1558           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
1559           SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
1560         },
1561         {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
1562          {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
1563           SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
1564           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
1565         },
1566         {HDMI_REF_266M_CLK_ROOT, IP_CLOCK_SLICE, 56,
1567          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
1568           SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_266M_CLK,
1569           SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
1570         },
1571         {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
1572          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1573           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1574           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1575         },
1576         {MEDIA_MIPI_PHY1_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
1577          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
1578           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1579           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1580         },
1581         {MEDIA_DISP1_PIX_CLK_ROOT, IP_CLOCK_SLICE, 60,
1582          {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
1583           AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
1584           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
1585         },
1586         {MEDIA_LDB_CLK_ROOT, IP_CLOCK_SLICE, 62,
1587          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
1588           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1589           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1590         },
1591         {MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 63,
1592          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
1593           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1594           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
1595         },
1596         {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
1597          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1598           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1599           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1600         },
1601         {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
1602          {DRAM_PLL1_CLK}
1603         },
1604         {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
1605          {ARM_A53_ALT_CLK, ARM_PLL_CLK}
1606         },
1607 };
1608 #endif
1609
1610 static int select(enum clk_root_index clock_id)
1611 {
1612         int i, size;
1613         struct clk_root_map *p = root_array;
1614
1615         size = ARRAY_SIZE(root_array);
1616
1617         for (i = 0; i < size; i++, p++) {
1618                 if (clock_id == p->entry)
1619                         return i;
1620         }
1621
1622         return -EINVAL;
1623 }
1624
1625 static void __iomem *get_clk_root_target(enum clk_slice_type slice_type,
1626                                          u32 slice_index)
1627 {
1628         void __iomem *clk_root_target;
1629
1630         switch (slice_type) {
1631         case CORE_CLOCK_SLICE:
1632                 clk_root_target =
1633                 (void __iomem *)&ccm_reg->core_root[slice_index];
1634                 break;
1635         case BUS_CLOCK_SLICE:
1636                 clk_root_target =
1637                         (void __iomem *)&ccm_reg->bus_root[slice_index];
1638                 break;
1639         case IP_CLOCK_SLICE:
1640                 clk_root_target =
1641                         (void __iomem *)&ccm_reg->ip_root[slice_index];
1642                 break;
1643         case AHB_CLOCK_SLICE:
1644                 clk_root_target =
1645                         (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2];
1646                 break;
1647         case IPG_CLOCK_SLICE:
1648                 clk_root_target =
1649                         (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2 + 1];
1650                 break;
1651         case CORE_SEL_CLOCK_SLICE:
1652                 clk_root_target = (void __iomem *)&ccm_reg->core_sel;
1653                 break;
1654         case DRAM_SEL_CLOCK_SLICE:
1655                 clk_root_target = (void __iomem *)&ccm_reg->dram_sel;
1656                 break;
1657         default:
1658                 return NULL;
1659         }
1660
1661         return clk_root_target;
1662 }
1663
1664 int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
1665 {
1666         int root_entry;
1667         struct clk_root_map *p;
1668         void __iomem *clk_root_target;
1669
1670         if (clock_id >= CLK_ROOT_MAX)
1671                 return -EINVAL;
1672
1673         root_entry = select(clock_id);
1674         if (root_entry < 0)
1675                 return -EINVAL;
1676
1677         p = &root_array[root_entry];
1678         clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1679         if (!clk_root_target)
1680                 return -EINVAL;
1681
1682         *val = readl(clk_root_target);
1683
1684         return 0;
1685 }
1686
1687 int clock_set_target_val(enum clk_root_index clock_id, u32 val)
1688 {
1689         int root_entry;
1690         struct clk_root_map *p;
1691         void __iomem *clk_root_target;
1692
1693         if (clock_id >= CLK_ROOT_MAX)
1694                 return -EINVAL;
1695
1696         root_entry = select(clock_id);
1697         if (root_entry < 0)
1698                 return -EINVAL;
1699
1700         p = &root_array[root_entry];
1701         clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1702         if (!clk_root_target)
1703                 return -EINVAL;
1704
1705         writel(val, clk_root_target);
1706
1707         return 0;
1708 }
1709
1710 int clock_root_enabled(enum clk_root_index clock_id)
1711 {
1712         void __iomem *clk_root_target;
1713         u32 slice_index, slice_type;
1714         u32 val;
1715         int root_entry;
1716
1717         if (clock_id >= CLK_ROOT_MAX)
1718                 return -EINVAL;
1719
1720         root_entry = select(clock_id);
1721         if (root_entry < 0)
1722                 return -EINVAL;
1723
1724         slice_type = root_array[root_entry].slice_type;
1725         slice_index = root_array[root_entry].slice_index;
1726
1727         if ((slice_type == IPG_CLOCK_SLICE) ||
1728             (slice_type == DRAM_SEL_CLOCK_SLICE) ||
1729             (slice_type == CORE_SEL_CLOCK_SLICE)) {
1730                 /*
1731                  * Not supported, from CCM doc
1732                  * TODO
1733                  */
1734                 return 0;
1735         }
1736
1737         clk_root_target = get_clk_root_target(slice_type, slice_index);
1738         if (!clk_root_target)
1739                 return -EINVAL;
1740
1741         val = readl(clk_root_target);
1742
1743         return (val & CLK_ROOT_ON) ? 1 : 0;
1744 }
1745
1746 /* CCGR CLK gate operation */
1747 int clock_enable(enum clk_ccgr_index index, bool enable)
1748 {
1749         void __iomem *ccgr;
1750
1751         if (index >= CCGR_MAX)
1752                 return -EINVAL;
1753
1754         if (enable)
1755                 ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_set;
1756         else
1757                 ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_clr;
1758
1759         writel(CCGR_CLK_ON_MASK, ccgr);
1760
1761         return 0;
1762 }
1763
1764 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
1765 {
1766         u32 val;
1767         int root_entry;
1768         struct clk_root_map *p;
1769         void __iomem *clk_root_target;
1770
1771         if (clock_id >= CLK_ROOT_MAX)
1772                 return -EINVAL;
1773
1774         root_entry = select(clock_id);
1775         if (root_entry < 0)
1776                 return -EINVAL;
1777
1778         p = &root_array[root_entry];
1779
1780         if ((p->slice_type == CORE_CLOCK_SLICE) ||
1781             (p->slice_type == IPG_CLOCK_SLICE) ||
1782             (p->slice_type == CORE_SEL_CLOCK_SLICE) ||
1783             (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
1784                 *pre_div = 0;
1785                 return 0;
1786         }
1787
1788         clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1789         if (!clk_root_target)
1790                 return -EINVAL;
1791
1792         val = readl(clk_root_target);
1793         val &= CLK_ROOT_PRE_DIV_MASK;
1794         val >>= CLK_ROOT_PRE_DIV_SHIFT;
1795
1796         *pre_div = val;
1797
1798         return 0;
1799 }
1800
1801 int clock_get_postdiv(enum clk_root_index clock_id,
1802                       enum root_post_div *post_div)
1803 {
1804         u32 val, mask;
1805         int root_entry;
1806         struct clk_root_map *p;
1807         void __iomem *clk_root_target;
1808
1809         if (clock_id >= CLK_ROOT_MAX)
1810                 return -EINVAL;
1811
1812         root_entry = select(clock_id);
1813         if (root_entry < 0)
1814                 return -EINVAL;
1815
1816         p = &root_array[root_entry];
1817
1818         if ((p->slice_type == CORE_SEL_CLOCK_SLICE) ||
1819             (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
1820                 *post_div = 0;
1821                 return 0;
1822         }
1823
1824         clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1825         if (!clk_root_target)
1826                 return -EINVAL;
1827
1828         if (p->slice_type == IPG_CLOCK_SLICE)
1829                 mask = CLK_ROOT_IPG_POST_DIV_MASK;
1830         else if (p->slice_type == CORE_CLOCK_SLICE)
1831                 mask = CLK_ROOT_CORE_POST_DIV_MASK;
1832         else
1833                 mask = CLK_ROOT_POST_DIV_MASK;
1834
1835         val = readl(clk_root_target);
1836         val &= mask;
1837         val >>= CLK_ROOT_POST_DIV_SHIFT;
1838
1839         *post_div = val;
1840
1841         return 0;
1842 }
1843
1844 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
1845 {
1846         u32 val;
1847         int root_entry;
1848         struct clk_root_map *p;
1849         void __iomem *clk_root_target;
1850
1851         if (clock_id >= CLK_ROOT_MAX)
1852                 return -EINVAL;
1853
1854         root_entry = select(clock_id);
1855         if (root_entry < 0)
1856                 return -EINVAL;
1857
1858         p = &root_array[root_entry];
1859
1860         clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1861         if (!clk_root_target)
1862                 return -EINVAL;
1863
1864         val = readl(clk_root_target);
1865         val &= CLK_ROOT_SRC_MUX_MASK;
1866         val >>= CLK_ROOT_SRC_MUX_SHIFT;
1867
1868         *p_clock_src = p->src_mux[val];
1869
1870         return 0;
1871 }