1 // SPDX-License-Identifier: GPL-2.0+
5 * Peng Fan <peng.fan@nxp.com>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/sys_proto.h>
15 #include <linux/iopoll.h>
17 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
19 static u32 get_root_clk(enum clk_root_index clock_id);
21 static u32 decode_frac_pll(enum clk_root_src frac_pll)
23 u32 pll_cfg0, pll_cfg1, pllout;
24 u32 pll_refclk_sel, pll_refclk;
25 u32 divr_val, divq_val, divf_val, divff, divfi;
26 u32 pllout_div_shift, pllout_div_mask, pllout_div;
30 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
31 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
32 pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
33 pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
36 printf("Frac PLL %d not supporte\n", frac_pll);
40 pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
41 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
44 if (pll_cfg0 & FRAC_PLL_PD_MASK)
47 /* output not enabled */
48 if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
51 pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
53 if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
54 pll_refclk = 25000000u;
55 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
56 pll_refclk = 27000000u;
57 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
58 pll_refclk = 27000000u;
62 if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
65 divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
66 FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
67 divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
69 divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
70 FRAC_PLL_FRAC_DIV_CTL_SHIFT;
71 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
73 divf_val = 1 + divfi + divff / (1 << 24);
75 pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
78 return pllout / (pllout_div + 1);
81 static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
83 u32 pll_cfg0, pll_cfg1, pll_cfg2;
84 u32 pll_refclk_sel, pll_refclk;
85 u32 divr1, divr2, divf1, divf2, divq, div;
88 u32 pllout_div_shift, pllout_div_mask, pllout_div;
92 case SYSTEM_PLL1_800M_CLK:
93 case SYSTEM_PLL1_400M_CLK:
94 case SYSTEM_PLL1_266M_CLK:
95 case SYSTEM_PLL1_200M_CLK:
96 case SYSTEM_PLL1_160M_CLK:
97 case SYSTEM_PLL1_133M_CLK:
98 case SYSTEM_PLL1_100M_CLK:
99 case SYSTEM_PLL1_80M_CLK:
100 case SYSTEM_PLL1_40M_CLK:
101 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
102 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
103 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
104 pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
105 pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
107 case SYSTEM_PLL2_1000M_CLK:
108 case SYSTEM_PLL2_500M_CLK:
109 case SYSTEM_PLL2_333M_CLK:
110 case SYSTEM_PLL2_250M_CLK:
111 case SYSTEM_PLL2_200M_CLK:
112 case SYSTEM_PLL2_166M_CLK:
113 case SYSTEM_PLL2_125M_CLK:
114 case SYSTEM_PLL2_100M_CLK:
115 case SYSTEM_PLL2_50M_CLK:
116 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
117 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
118 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
119 pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
120 pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
122 case SYSTEM_PLL3_CLK:
123 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
124 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
125 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
126 pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
127 pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
130 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
131 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
132 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
133 pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
134 pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
137 printf("sscg pll %d not supporte\n", sscg_pll);
143 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
146 case SYSTEM_PLL3_CLK:
147 pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
150 case SYSTEM_PLL2_1000M_CLK:
151 case SYSTEM_PLL1_800M_CLK:
152 pll_clke = SSCG_PLL_CLKE_MASK;
155 case SYSTEM_PLL2_500M_CLK:
156 case SYSTEM_PLL1_400M_CLK:
157 pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
160 case SYSTEM_PLL2_333M_CLK:
161 case SYSTEM_PLL1_266M_CLK:
162 pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
165 case SYSTEM_PLL2_250M_CLK:
166 case SYSTEM_PLL1_200M_CLK:
167 pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
170 case SYSTEM_PLL2_200M_CLK:
171 case SYSTEM_PLL1_160M_CLK:
172 pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
175 case SYSTEM_PLL2_166M_CLK:
176 case SYSTEM_PLL1_133M_CLK:
177 pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
180 case SYSTEM_PLL2_125M_CLK:
181 case SYSTEM_PLL1_100M_CLK:
182 pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
185 case SYSTEM_PLL2_100M_CLK:
186 case SYSTEM_PLL1_80M_CLK:
187 pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
190 case SYSTEM_PLL2_50M_CLK:
191 case SYSTEM_PLL1_40M_CLK:
192 pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
196 printf("sscg pll %d not supporte\n", sscg_pll);
201 if (pll_cfg0 & SSCG_PLL_PD_MASK)
204 /* output not enabled */
205 if ((pll_cfg0 & pll_clke) == 0)
208 pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
209 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
211 pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
213 if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
214 pll_refclk = 25000000u;
215 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
216 pll_refclk = 27000000u;
217 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
218 pll_refclk = 27000000u;
222 /* We assume bypass1/2 are the same value */
223 if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
224 (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
227 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
228 SSCG_PLL_REF_DIVR1_SHIFT;
229 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
230 SSCG_PLL_REF_DIVR2_SHIFT;
231 divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
232 SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
233 divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
234 SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
235 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
236 SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
237 sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
244 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
245 (divr2 + 1) * (divf2 + 1) / (divq + 1);
247 return pllout / (pllout_div + 1) / div;
250 static u32 get_root_src_clk(enum clk_root_src root_src)
260 return decode_frac_pll(root_src);
261 case SYSTEM_PLL1_800M_CLK:
262 case SYSTEM_PLL1_400M_CLK:
263 case SYSTEM_PLL1_266M_CLK:
264 case SYSTEM_PLL1_200M_CLK:
265 case SYSTEM_PLL1_160M_CLK:
266 case SYSTEM_PLL1_133M_CLK:
267 case SYSTEM_PLL1_100M_CLK:
268 case SYSTEM_PLL1_80M_CLK:
269 case SYSTEM_PLL1_40M_CLK:
270 case SYSTEM_PLL2_1000M_CLK:
271 case SYSTEM_PLL2_500M_CLK:
272 case SYSTEM_PLL2_333M_CLK:
273 case SYSTEM_PLL2_250M_CLK:
274 case SYSTEM_PLL2_200M_CLK:
275 case SYSTEM_PLL2_166M_CLK:
276 case SYSTEM_PLL2_125M_CLK:
277 case SYSTEM_PLL2_100M_CLK:
278 case SYSTEM_PLL2_50M_CLK:
279 case SYSTEM_PLL3_CLK:
280 return decode_sscg_pll(root_src);
281 case ARM_A53_ALT_CLK:
282 return get_root_clk(ARM_A53_CLK_ROOT);
290 static u32 get_root_clk(enum clk_root_index clock_id)
292 enum clk_root_src root_src;
293 u32 post_podf, pre_podf, root_src_clk;
295 if (clock_root_enabled(clock_id) <= 0)
298 if (clock_get_prediv(clock_id, &pre_podf) < 0)
301 if (clock_get_postdiv(clock_id, &post_podf) < 0)
304 if (clock_get_src(clock_id, &root_src) < 0)
307 root_src_clk = get_root_src_clk(root_src);
309 return root_src_clk / (post_podf + 1) / (pre_podf + 1);
312 #ifdef CONFIG_MXC_OCOTP
313 void enable_ocotp_clk(unsigned char enable)
315 clock_enable(CCGR_OCOTP, !!enable);
319 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
321 /* 0 - 3 is valid i2c num */
325 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
330 u32 get_arm_core_clk(void)
332 enum clk_root_src root_src;
335 if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
338 root_src_clk = get_root_src_clk(root_src);
343 unsigned int mxc_get_clock(enum mxc_clock clk)
349 return get_arm_core_clk();
351 clock_get_target_val(IPG_CLK_ROOT, &val);
353 return get_root_clk(AHB_CLK_ROOT) / (val + 1);
355 return get_root_clk(USDHC1_CLK_ROOT);
357 return get_root_clk(USDHC2_CLK_ROOT);
359 return get_root_clk(clk);
363 u32 imx_get_uartclk(void)
365 return mxc_get_clock(UART1_CLK_ROOT);
368 void mxs_set_lcdclk(u32 base_addr, u32 freq)
371 * LCDIF_PIXEL_CLK: select 800MHz root clock,
372 * select pre divider 8, output is 100 MHz
374 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
375 CLK_ROOT_SOURCE_SEL(4) |
376 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
379 void init_wdog_clk(void)
381 clock_enable(CCGR_WDOG1, 0);
382 clock_enable(CCGR_WDOG2, 0);
383 clock_enable(CCGR_WDOG3, 0);
384 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
385 CLK_ROOT_SOURCE_SEL(0));
386 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
387 CLK_ROOT_SOURCE_SEL(0));
388 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
389 CLK_ROOT_SOURCE_SEL(0));
390 clock_enable(CCGR_WDOG1, 1);
391 clock_enable(CCGR_WDOG2, 1);
392 clock_enable(CCGR_WDOG3, 1);
396 void init_nand_clk(void)
398 clock_enable(CCGR_RAWNAND, 0);
399 clock_set_target_val(NAND_CLK_ROOT,
400 CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
401 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
402 clock_enable(CCGR_RAWNAND, 1);
405 void init_uart_clk(u32 index)
407 /* Set uart clock root 25M OSC */
410 clock_enable(CCGR_UART1, 0);
411 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
412 CLK_ROOT_SOURCE_SEL(0));
413 clock_enable(CCGR_UART1, 1);
416 clock_enable(CCGR_UART2, 0);
417 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
418 CLK_ROOT_SOURCE_SEL(0));
419 clock_enable(CCGR_UART2, 1);
422 clock_enable(CCGR_UART3, 0);
423 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
424 CLK_ROOT_SOURCE_SEL(0));
425 clock_enable(CCGR_UART3, 1);
428 clock_enable(CCGR_UART4, 0);
429 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
430 CLK_ROOT_SOURCE_SEL(0));
431 clock_enable(CCGR_UART4, 1);
434 printf("Invalid uart index\n");
439 void init_clk_usdhc(u32 index)
442 * set usdhc clock root
447 clock_enable(CCGR_USDHC1, 0);
448 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
449 CLK_ROOT_SOURCE_SEL(1));
450 clock_enable(CCGR_USDHC1, 1);
453 clock_enable(CCGR_USDHC2, 0);
454 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
455 CLK_ROOT_SOURCE_SEL(1));
456 clock_enable(CCGR_USDHC2, 1);
459 printf("Invalid usdhc index\n");
464 int set_clk_qspi(void)
470 clock_enable(CCGR_QSPI, 0);
471 clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
472 CLK_ROOT_SOURCE_SEL(7));
473 clock_enable(CCGR_QSPI, 1);
478 #ifdef CONFIG_FEC_MXC
479 int set_clk_enet(enum enet_freq type)
486 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
489 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
492 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
498 /* disable the clock first */
499 clock_enable(CCGR_ENET1, 0);
500 clock_enable(CCGR_SIM_ENET, 0);
502 /* set enet axi clock 266Mhz */
503 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
504 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
505 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
506 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
508 target = CLK_ROOT_ON | enet1_ref |
509 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
510 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
511 clock_set_target_val(ENET_REF_CLK_ROOT, target);
513 target = CLK_ROOT_ON |
514 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
515 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
516 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
517 clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
520 clock_enable(CCGR_SIM_ENET, 1);
521 clock_enable(CCGR_ENET1, 1);
527 u32 imx_get_fecclk(void)
529 return get_root_clk(ENET_AXI_CLK_ROOT);
532 static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
533 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
535 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
537 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
541 void dram_enable_bypass(ulong clk_val)
544 struct dram_bypass_clk_setting *config;
546 for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
547 if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
551 if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
552 printf("No matched freq table %lu\n", clk_val);
556 config = &imx8mq_dram_bypass_tbl[i];
558 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
559 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
560 CLK_ROOT_PRE_DIV(config->alt_pre_div));
561 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
562 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
563 CLK_ROOT_PRE_DIV(config->apb_pre_div));
564 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
565 CLK_ROOT_SOURCE_SEL(1));
568 void dram_disable_bypass(void)
570 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
571 CLK_ROOT_SOURCE_SEL(0));
572 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
573 CLK_ROOT_SOURCE_SEL(4) |
574 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
577 #ifdef CONFIG_SPL_BUILD
578 void dram_pll_init(ulong pll_val)
581 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
582 void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
585 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
586 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
590 val = readl(pll_cfg_reg2);
591 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
592 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
593 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
594 SSCG_PLL_REF_DIVR2_MASK);
595 val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
596 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
597 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
598 val |= SSCG_PLL_REF_DIVR2_VAL(29);
599 writel(val, pll_cfg_reg2);
602 val = readl(pll_cfg_reg2);
603 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
604 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
605 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
606 SSCG_PLL_REF_DIVR2_MASK);
607 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
608 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
609 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
610 val |= SSCG_PLL_REF_DIVR2_VAL(29);
611 writel(val, pll_cfg_reg2);
614 val = readl(pll_cfg_reg2);
615 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
616 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
617 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
618 SSCG_PLL_REF_DIVR2_MASK);
619 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
620 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
621 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
622 val |= SSCG_PLL_REF_DIVR2_VAL(29);
623 writel(val, pll_cfg_reg2);
626 val = readl(pll_cfg_reg2);
627 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
628 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
629 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
630 SSCG_PLL_REF_DIVR2_MASK);
631 val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
632 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
633 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
634 val |= SSCG_PLL_REF_DIVR2_VAL(30);
635 writel(val, pll_cfg_reg2);
641 /* Clear power down bit */
642 clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
643 /* Eanble ARM_PLL/SYS_PLL */
644 setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
647 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
649 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
651 while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
655 static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
657 void __iomem *pll_cfg0, __iomem *pll_cfg1;
658 u32 val_cfg0, val_cfg1, divq;
663 pll_cfg0 = &ana_pll->arm_pll_cfg0;
664 pll_cfg1 = &ana_pll->arm_pll_cfg1;
666 if (val == FRAC_PLL_OUT_1000M) {
667 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
670 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
673 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
674 FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
675 FRAC_PLL_REFCLK_DIV_VAL(4) |
676 FRAC_PLL_OUTPUT_DIV_VAL(divq);
682 /* bypass the clock */
683 setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
685 writel(val_cfg1, pll_cfg1);
686 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
687 val_cfg0 = readl(pll_cfg0);
688 /* unbypass the clock */
689 clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
690 ret = readl_poll_timeout(pll_cfg0, val_cfg0,
691 val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
693 printf("%s timeout\n", __func__);
694 clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
704 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
705 CLK_ROOT_SOURCE_SEL(0));
708 * 8MQ only supports two grades: consumer and industrial.
709 * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
711 grade = get_cpu_temp_grade(NULL, NULL);
713 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
715 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_800M);
717 /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
718 clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
721 * According to ANAMIX SPEC
722 * sys pll1 fixed at 800MHz
723 * sys pll2 fixed at 1GHz
724 * Here we only enable the outputs.
726 setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
727 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
728 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
729 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
730 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
732 setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
733 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
734 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
735 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
736 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
738 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
739 CLK_ROOT_SOURCE_SEL(1));
742 clock_enable(CCGR_TSENSOR, 1);
743 clock_enable(CCGR_OCOTP, 1);
745 /* config GIC ROOT to sys_pll2_200m */
746 clock_enable(CCGR_GIC, 0);
747 clock_set_target_val(GIC_CLK_ROOT,
748 CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
749 clock_enable(CCGR_GIC, 1);
758 #ifndef CONFIG_SPL_BUILD
759 static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
764 freq = decode_frac_pll(ARM_PLL_CLK);
765 printf("ARM_PLL %8d MHz\n", freq / 1000000);
766 freq = decode_sscg_pll(DRAM_PLL1_CLK);
767 printf("DRAM_PLL %8d MHz\n", freq / 1000000);
768 freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
769 printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
770 freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
771 printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
772 freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
773 printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
774 freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
775 printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
776 freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
777 printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
778 freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
779 printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
780 freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
781 printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
782 freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
783 printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
784 freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
785 printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
786 freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
787 printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
788 freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
789 printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
790 freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
791 printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
792 freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
793 printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
794 freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
795 printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
796 freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
797 printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
798 freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
799 printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
800 freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
801 printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
802 freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
803 printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
804 freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
805 printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
806 freq = mxc_get_clock(UART1_CLK_ROOT);
807 printf("UART1 %8d MHz\n", freq / 1000000);
808 freq = mxc_get_clock(USDHC1_CLK_ROOT);
809 printf("USDHC1 %8d MHz\n", freq / 1000000);
810 freq = mxc_get_clock(QSPI_CLK_ROOT);
811 printf("QSPI %8d MHz\n", freq / 1000000);
816 clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,