arch/arm/mach-imx/imx8m/clock_imx8mm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/io.h>
  13 #include <div64.h>
  14 #include <errno.h>
  15 #include <linux/bitops.h>
  16 #include <linux/delay.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  21
  22 void enable_ocotp_clk(unsigned char enable)
  23 {
  24         clock_enable(CCGR_OCOTP, !!enable);
  25 }
  26
  27 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  28 {
  29         /* 0 - 3 is valid i2c num */
  30         if (i2c_num > 3)
  31                 return -EINVAL;
  32
  33         clock_enable(CCGR_I2C1 + i2c_num, !!enable);
  34
  35         return 0;
  36 }
  37
  38 #ifdef CONFIG_SPL_BUILD
  39 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
  40         PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
  41         PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
  42         PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
  43         PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  44         PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
  45         PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
  46         PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
  47         PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
  48         PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
  49         PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
  50 };
  51
  52 static int fracpll_configure(enum pll_clocks pll, u32 freq)
  53 {
  54         int i;
  55         u32 tmp, div_val;
  56         void *pll_base;
  57         struct imx_int_pll_rate_table *rate;
  58
  59         for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
  60                 if (freq == imx8mm_fracpll_tbl[i].rate)
  61                         break;
  62         }
  63
  64         if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
  65                 printf("No matched freq table %u\n", freq);
  66                 return -EINVAL;
  67         }
  68
  69         rate = &imx8mm_fracpll_tbl[i];
  70
  71         switch (pll) {
  72         case ANATOP_DRAM_PLL:
  73                 setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
  74                 setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
  75                 writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
  76
  77                 pll_base = &ana_pll->dram_pll_gnrl_ctl;
  78                 break;
  79         case ANATOP_VIDEO_PLL:
  80                 pll_base = &ana_pll->video_pll1_gnrl_ctl;
  81                 break;
  82         default:
  83                 return 0;
  84         }
  85         /* Bypass clock and set lock to pll output lock */
  86         tmp = readl(pll_base);
  87         tmp |= BYPASS_MASK;
  88         writel(tmp, pll_base);
  89
  90         /* Enable RST */
  91         tmp &= ~RST_MASK;
  92         writel(tmp, pll_base);
  93
  94         div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
  95                 (rate->sdiv << SDIV_SHIFT);
  96         writel(div_val, pll_base + 4);
  97         writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
  98
  99         __udelay(100);
 100
 101         /* Disable RST */
 102         tmp |= RST_MASK;
 103         writel(tmp, pll_base);
 104
 105         /* Wait Lock*/
 106         while (!(readl(pll_base) & LOCK_STATUS))
 107                 ;
 108
 109         /* Bypass */
 110         tmp &= ~BYPASS_MASK;
 111         writel(tmp, pll_base);
 112
 113         return 0;
 114 }
 115
 116 void dram_pll_init(ulong pll_val)
 117 {
 118         fracpll_configure(ANATOP_DRAM_PLL, pll_val);
 119 }
 120
 121 static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
 122         DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
 123                                 CLK_ROOT_PRE_DIV2),
 124         DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
 125                                 CLK_ROOT_PRE_DIV2),
 126         DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
 127                                 CLK_ROOT_PRE_DIV2),
 128 };
 129
 130 void dram_enable_bypass(ulong clk_val)
 131 {
 132         int i;
 133         struct dram_bypass_clk_setting *config;
 134
 135         for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
 136                 if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
 137                         break;
 138         }
 139
 140         if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
 141                 printf("No matched freq table %lu\n", clk_val);
 142                 return;
 143         }
 144
 145         config = &imx8mm_dram_bypass_tbl[i];
 146
 147         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 148                              CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
 149                              CLK_ROOT_PRE_DIV(config->alt_pre_div));
 150         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 151                              CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
 152                              CLK_ROOT_PRE_DIV(config->apb_pre_div));
 153         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 154                              CLK_ROOT_SOURCE_SEL(1));
 155 }
 156
 157 void dram_disable_bypass(void)
 158 {
 159         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 160                              CLK_ROOT_SOURCE_SEL(0));
 161         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 162                              CLK_ROOT_SOURCE_SEL(4) |
 163                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
 164 }
 165 #endif
 166
 167 void init_uart_clk(u32 index)
 168 {
 169         /*
 170          * set uart clock root
 171          * 24M OSC
 172          */
 173         switch (index) {
 174         case 0:
 175                 clock_enable(CCGR_UART1, 0);
 176                 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
 177                                      CLK_ROOT_SOURCE_SEL(0));
 178                 clock_enable(CCGR_UART1, 1);
 179                 return;
 180         case 1:
 181                 clock_enable(CCGR_UART2, 0);
 182                 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
 183                                      CLK_ROOT_SOURCE_SEL(0));
 184                 clock_enable(CCGR_UART2, 1);
 185                 return;
 186         case 2:
 187                 clock_enable(CCGR_UART3, 0);
 188                 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
 189                                      CLK_ROOT_SOURCE_SEL(0));
 190                 clock_enable(CCGR_UART3, 1);
 191                 return;
 192         case 3:
 193                 clock_enable(CCGR_UART4, 0);
 194                 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
 195                                      CLK_ROOT_SOURCE_SEL(0));
 196                 clock_enable(CCGR_UART4, 1);
 197                 return;
 198         default:
 199                 printf("Invalid uart index\n");
 200                 return;
 201         }
 202 }
 203
 204 void init_wdog_clk(void)
 205 {
 206         clock_enable(CCGR_WDOG1, 0);
 207         clock_enable(CCGR_WDOG2, 0);
 208         clock_enable(CCGR_WDOG3, 0);
 209         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 210                              CLK_ROOT_SOURCE_SEL(0));
 211         clock_enable(CCGR_WDOG1, 1);
 212         clock_enable(CCGR_WDOG2, 1);
 213         clock_enable(CCGR_WDOG3, 1);
 214 }
 215
 216 int clock_init(void)
 217 {
 218         u32 val_cfg0;
 219
 220         /*
 221          * The gate is not exported to clk tree, so configure them here.
 222          * According to ANAMIX SPEC
 223          * sys pll1 fixed at 800MHz
 224          * sys pll2 fixed at 1GHz
 225          * Here we only enable the outputs.
 226          */
 227         val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
 228         val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 229                 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
 230                 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
 231                 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
 232                 INTPLL_DIV20_CLKE_MASK;
 233         writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
 234
 235         val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
 236         val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 237                 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
 238                 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
 239                 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
 240                 INTPLL_DIV20_CLKE_MASK;
 241         writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
 242
 243         /* config GIC to sys_pll2_100m */
 244         clock_enable(CCGR_GIC, 0);
 245         clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
 246                              CLK_ROOT_SOURCE_SEL(3));
 247         clock_enable(CCGR_GIC, 1);
 248
 249         clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
 250                              CLK_ROOT_SOURCE_SEL(1));
 251
 252         clock_enable(CCGR_DDR1, 0);
 253         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 254                              CLK_ROOT_SOURCE_SEL(1));
 255         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 256                              CLK_ROOT_SOURCE_SEL(1));
 257         clock_enable(CCGR_DDR1, 1);
 258
 259         init_wdog_clk();
 260
 261         clock_enable(CCGR_TEMP_SENSOR, 1);
 262
 263         clock_enable(CCGR_SEC_DEBUG, 1);
 264
 265         return 0;
 266 };
 267
 268 u32 imx_get_uartclk(void)
 269 {
 270         return 24000000U;
 271 }
 272
 273 static u32 decode_intpll(enum clk_root_src intpll)
 274 {
 275         u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
 276         u32 main_div, pre_div, post_div, div;
 277         u64 freq;
 278
 279         switch (intpll) {
 280         case ARM_PLL_CLK:
 281                 pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
 282                 pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
 283                 break;
 284         case GPU_PLL_CLK:
 285                 pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
 286                 pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
 287                 break;
 288         case VPU_PLL_CLK:
 289                 pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
 290                 pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
 291                 break;
 292         case SYSTEM_PLL1_800M_CLK:
 293         case SYSTEM_PLL1_400M_CLK:
 294         case SYSTEM_PLL1_266M_CLK:
 295         case SYSTEM_PLL1_200M_CLK:
 296         case SYSTEM_PLL1_160M_CLK:
 297         case SYSTEM_PLL1_133M_CLK:
 298         case SYSTEM_PLL1_100M_CLK:
 299         case SYSTEM_PLL1_80M_CLK:
 300         case SYSTEM_PLL1_40M_CLK:
 301                 pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
 302                 pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
 303                 break;
 304         case SYSTEM_PLL2_1000M_CLK:
 305         case SYSTEM_PLL2_500M_CLK:
 306         case SYSTEM_PLL2_333M_CLK:
 307         case SYSTEM_PLL2_250M_CLK:
 308         case SYSTEM_PLL2_200M_CLK:
 309         case SYSTEM_PLL2_166M_CLK:
 310         case SYSTEM_PLL2_125M_CLK:
 311         case SYSTEM_PLL2_100M_CLK:
 312         case SYSTEM_PLL2_50M_CLK:
 313                 pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
 314                 pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
 315                 break;
 316         case SYSTEM_PLL3_CLK:
 317                 pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
 318                 pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
 319                 break;
 320         default:
 321                 return -EINVAL;
 322         }
 323
 324         /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
 325         if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
 326                 return 0;
 327
 328         if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
 329                 return 0;
 330
 331         /*
 332          * When BYPASS is equal to 1, PLL enters the bypass mode
 333          * regardless of the values of RESETB
 334          */
 335         if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
 336                 return 24000000u;
 337
 338         if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
 339                 puts("pll not locked\n");
 340                 return 0;
 341         }
 342
 343         switch (intpll) {
 344         case ARM_PLL_CLK:
 345         case GPU_PLL_CLK:
 346         case VPU_PLL_CLK:
 347         case SYSTEM_PLL3_CLK:
 348         case SYSTEM_PLL1_800M_CLK:
 349         case SYSTEM_PLL2_1000M_CLK:
 350                 pll_clke_mask = INTPLL_CLKE_MASK;
 351                 div = 1;
 352                 break;
 353
 354         case SYSTEM_PLL1_400M_CLK:
 355         case SYSTEM_PLL2_500M_CLK:
 356                 pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
 357                 div = 2;
 358                 break;
 359
 360         case SYSTEM_PLL1_266M_CLK:
 361         case SYSTEM_PLL2_333M_CLK:
 362                 pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
 363                 div = 3;
 364                 break;
 365
 366         case SYSTEM_PLL1_200M_CLK:
 367         case SYSTEM_PLL2_250M_CLK:
 368                 pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
 369                 div = 4;
 370                 break;
 371
 372         case SYSTEM_PLL1_160M_CLK:
 373         case SYSTEM_PLL2_200M_CLK:
 374                 pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
 375                 div = 5;
 376                 break;
 377
 378         case SYSTEM_PLL1_133M_CLK:
 379         case SYSTEM_PLL2_166M_CLK:
 380                 pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
 381                 div = 6;
 382                 break;
 383
 384         case SYSTEM_PLL1_100M_CLK:
 385         case SYSTEM_PLL2_125M_CLK:
 386                 pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
 387                 div = 8;
 388                 break;
 389
 390         case SYSTEM_PLL1_80M_CLK:
 391         case SYSTEM_PLL2_100M_CLK:
 392                 pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
 393                 div = 10;
 394                 break;
 395
 396         case SYSTEM_PLL1_40M_CLK:
 397         case SYSTEM_PLL2_50M_CLK:
 398                 pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
 399                 div = 20;
 400                 break;
 401         default:
 402                 return -EINVAL;
 403         }
 404
 405         if ((pll_gnrl_ctl & pll_clke_mask) == 0)
 406                 return 0;
 407
 408         main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
 409                 INTPLL_MAIN_DIV_SHIFT;
 410         pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
 411                 INTPLL_PRE_DIV_SHIFT;
 412         post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
 413                 INTPLL_POST_DIV_SHIFT;
 414
 415         /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
 416         freq = 24000000ULL * main_div;
 417         return lldiv(freq, pre_div * (1 << post_div) * div);
 418 }
 419
 420 static u32 decode_fracpll(enum clk_root_src frac_pll)
 421 {
 422         u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
 423         u32 main_div, pre_div, post_div, k;
 424
 425         switch (frac_pll) {
 426         case DRAM_PLL1_CLK:
 427                 pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
 428                 pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
 429                 pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
 430                 break;
 431         case AUDIO_PLL1_CLK:
 432                 pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
 433                 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
 434                 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1);
 435                 break;
 436         case AUDIO_PLL2_CLK:
 437                 pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
 438                 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
 439                 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1);
 440                 break;
 441         case VIDEO_PLL_CLK:
 442                 pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
 443                 pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
 444                 pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
 445                 break;
 446         default:
 447                 printf("Not supported\n");
 448                 return 0;
 449         }
 450
 451         /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
 452         if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
 453                 return 0;
 454
 455         if ((pll_gnrl_ctl & RST_MASK) == 0)
 456                 return 0;
 457         /*
 458          * When BYPASS is equal to 1, PLL enters the bypass mode
 459          * regardless of the values of RESETB
 460          */
 461         if (pll_gnrl_ctl & BYPASS_MASK)
 462                 return 24000000u;
 463
 464         if (!(pll_gnrl_ctl & LOCK_STATUS)) {
 465                 puts("pll not locked\n");
 466                 return 0;
 467         }
 468
 469         if (!(pll_gnrl_ctl & CLKE_MASK))
 470                 return 0;
 471
 472         main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
 473                 MDIV_SHIFT;
 474         pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
 475                 PDIV_SHIFT;
 476         post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
 477                 SDIV_SHIFT;
 478
 479         k = pll_fdiv_ctl1 & KDIV_MASK;
 480
 481         return lldiv((main_div * 65536 + k) * 24000000ULL,
 482                      65536 * pre_div * (1 << post_div));
 483 }
 484
 485 static u32 get_root_src_clk(enum clk_root_src root_src)
 486 {
 487         switch (root_src) {
 488         case OSC_24M_CLK:
 489                 return 24000000u;
 490         case OSC_HDMI_CLK:
 491                 return 26000000u;
 492         case OSC_32K_CLK:
 493                 return 32000u;
 494         case ARM_PLL_CLK:
 495         case GPU_PLL_CLK:
 496         case VPU_PLL_CLK:
 497         case SYSTEM_PLL1_800M_CLK:
 498         case SYSTEM_PLL1_400M_CLK:
 499         case SYSTEM_PLL1_266M_CLK:
 500         case SYSTEM_PLL1_200M_CLK:
 501         case SYSTEM_PLL1_160M_CLK:
 502         case SYSTEM_PLL1_133M_CLK:
 503         case SYSTEM_PLL1_100M_CLK:
 504         case SYSTEM_PLL1_80M_CLK:
 505         case SYSTEM_PLL1_40M_CLK:
 506         case SYSTEM_PLL2_1000M_CLK:
 507         case SYSTEM_PLL2_500M_CLK:
 508         case SYSTEM_PLL2_333M_CLK:
 509         case SYSTEM_PLL2_250M_CLK:
 510         case SYSTEM_PLL2_200M_CLK:
 511         case SYSTEM_PLL2_166M_CLK:
 512         case SYSTEM_PLL2_125M_CLK:
 513         case SYSTEM_PLL2_100M_CLK:
 514         case SYSTEM_PLL2_50M_CLK:
 515         case SYSTEM_PLL3_CLK:
 516                 return decode_intpll(root_src);
 517         case DRAM_PLL1_CLK:
 518         case AUDIO_PLL1_CLK:
 519         case AUDIO_PLL2_CLK:
 520         case VIDEO_PLL_CLK:
 521                 return decode_fracpll(root_src);
 522         default:
 523                 return 0;
 524         }
 525
 526         return 0;
 527 }
 528
 529 static u32 get_root_clk(enum clk_root_index clock_id)
 530 {
 531         enum clk_root_src root_src;
 532         u32 post_podf, pre_podf, root_src_clk;
 533
 534         if (clock_root_enabled(clock_id) <= 0)
 535                 return 0;
 536
 537         if (clock_get_prediv(clock_id, &pre_podf) < 0)
 538                 return 0;
 539
 540         if (clock_get_postdiv(clock_id, &post_podf) < 0)
 541                 return 0;
 542
 543         if (clock_get_src(clock_id, &root_src) < 0)
 544                 return 0;
 545
 546         root_src_clk = get_root_src_clk(root_src);
 547
 548         return root_src_clk / (post_podf + 1) / (pre_podf + 1);
 549 }
 550
 551 u32 mxc_get_clock(enum mxc_clock clk)
 552 {
 553         u32 val;
 554
 555         switch (clk) {
 556         case MXC_ARM_CLK:
 557                 return get_root_clk(ARM_A53_CLK_ROOT);
 558         case MXC_IPG_CLK:
 559                 clock_get_target_val(IPG_CLK_ROOT, &val);
 560                 val = val & 0x3;
 561                 return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
 562         case MXC_CSPI_CLK:
 563                 return get_root_clk(ECSPI1_CLK_ROOT);
 564         case MXC_ESDHC_CLK:
 565                 return get_root_clk(USDHC1_CLK_ROOT);
 566         case MXC_ESDHC2_CLK:
 567                 return get_root_clk(USDHC2_CLK_ROOT);
 568         case MXC_ESDHC3_CLK:
 569                 return get_root_clk(USDHC3_CLK_ROOT);
 570         case MXC_I2C_CLK:
 571                 return get_root_clk(I2C1_CLK_ROOT);
 572         case MXC_UART_CLK:
 573                 return get_root_clk(UART1_CLK_ROOT);
 574         case MXC_QSPI_CLK:
 575                 return get_root_clk(QSPI_CLK_ROOT);
 576         default:
 577                 printf("Unsupported mxc_clock %d\n", clk);
 578                 break;
 579         }
 580
 581         return 0;
 582 }
 583
 584 #ifdef CONFIG_FEC_MXC
 585 int set_clk_enet(enum enet_freq type)
 586 {
 587         u32 target;
 588         u32 enet1_ref;
 589
 590         switch (type) {
 591         case ENET_125MHZ:
 592                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
 593                 break;
 594         case ENET_50MHZ:
 595                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
 596                 break;
 597         case ENET_25MHZ:
 598                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
 599                 break;
 600         default:
 601                 return -EINVAL;
 602         }
 603
 604         /* disable the clock first */
 605         clock_enable(CCGR_ENET1, 0);
 606         clock_enable(CCGR_SIM_ENET, 0);
 607
 608         /* set enet axi clock 266Mhz */
 609         target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
 610                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 611                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 612         clock_set_target_val(ENET_AXI_CLK_ROOT, target);
 613
 614         target = CLK_ROOT_ON | enet1_ref |
 615                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 616                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 617         clock_set_target_val(ENET_REF_CLK_ROOT, target);
 618
 619         target = CLK_ROOT_ON |
 620                 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
 621                 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 622                 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 623         clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
 624
 625         /* enable clock */
 626         clock_enable(CCGR_SIM_ENET, 1);
 627         clock_enable(CCGR_ENET1, 1);
 628
 629         return 0;
 630 }
 631 #endif