arch/arm/mach-imx/imx8/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <cpu.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <init.h>
  12 #include <asm/cache.h>
  13 #include <dm/device-internal.h>
  14 #include <dm/lists.h>
  15 #include <dm/uclass.h>
  16 #include <errno.h>
  17 #include <spl.h>
  18 #include <thermal.h>
  19 #include <asm/arch/sci/sci.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/arch-imx/cpu.h>
  22 #include <asm/armv8/cpu.h>
  23 #include <asm/armv8/mmu.h>
  24 #include <asm/setup.h>
  25 #include <asm/mach-imx/boot_mode.h>
  26 #include <spl.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #define BT_PASSOVER_TAG 0x504F
  31 struct pass_over_info_t *get_pass_over_info(void)
  32 {
  33         struct pass_over_info_t *p =
  34                 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
  35
  36         if (p->barker != BT_PASSOVER_TAG ||
  37             p->len != sizeof(struct pass_over_info_t))
  38                 return NULL;
  39
  40         return p;
  41 }
  42
  43 int arch_cpu_init(void)
  44 {
  45 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
  46         spl_save_restore_data();
  47 #endif
  48
  49 #ifdef CONFIG_SPL_BUILD
  50         struct pass_over_info_t *pass_over;
  51
  52         if (is_soc_rev(CHIP_REV_A)) {
  53                 pass_over = get_pass_over_info();
  54                 if (pass_over && pass_over->g_ap_mu == 0) {
  55                         /*
  56                          * When ap_mu is 0, means the U-Boot booted
  57                          * from first container
  58                          */
  59                         sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
  60                 }
  61         }
  62 #endif
  63
  64         return 0;
  65 }
  66
  67 int arch_cpu_init_dm(void)
  68 {
  69         struct udevice *devp;
  70         int node, ret;
  71
  72         node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
  73
  74         ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
  75         if (ret) {
  76                 printf("could not get scu %d\n", ret);
  77                 return ret;
  78         }
  79
  80         if (is_imx8qm()) {
  81                 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
  82                                                     SC_PM_PW_MODE_ON);
  83                 if (ret)
  84                         return ret;
  85         }
  86
  87         return 0;
  88 }
  89
  90 int print_bootinfo(void)
  91 {
  92         enum boot_device bt_dev = get_boot_device();
  93
  94         puts("Boot:  ");
  95         switch (bt_dev) {
  96         case SD1_BOOT:
  97                 puts("SD0\n");
  98                 break;
  99         case SD2_BOOT:
 100                 puts("SD1\n");
 101                 break;
 102         case SD3_BOOT:
 103                 puts("SD2\n");
 104                 break;
 105         case MMC1_BOOT:
 106                 puts("MMC0\n");
 107                 break;
 108         case MMC2_BOOT:
 109                 puts("MMC1\n");
 110                 break;
 111         case MMC3_BOOT:
 112                 puts("MMC2\n");
 113                 break;
 114         case FLEXSPI_BOOT:
 115                 puts("FLEXSPI\n");
 116                 break;
 117         case SATA_BOOT:
 118                 puts("SATA\n");
 119                 break;
 120         case NAND_BOOT:
 121                 puts("NAND\n");
 122                 break;
 123         case USB_BOOT:
 124                 puts("USB\n");
 125                 break;
 126         default:
 127                 printf("Unknown device %u\n", bt_dev);
 128                 break;
 129         }
 130
 131         return 0;
 132 }
 133
 134 enum boot_device get_boot_device(void)
 135 {
 136         enum boot_device boot_dev = SD1_BOOT;
 137
 138         sc_rsrc_t dev_rsrc;
 139
 140         sc_misc_get_boot_dev(-1, &dev_rsrc);
 141
 142         switch (dev_rsrc) {
 143         case SC_R_SDHC_0:
 144                 boot_dev = MMC1_BOOT;
 145                 break;
 146         case SC_R_SDHC_1:
 147                 boot_dev = SD2_BOOT;
 148                 break;
 149         case SC_R_SDHC_2:
 150                 boot_dev = SD3_BOOT;
 151                 break;
 152         case SC_R_NAND:
 153                 boot_dev = NAND_BOOT;
 154                 break;
 155         case SC_R_FSPI_0:
 156                 boot_dev = FLEXSPI_BOOT;
 157                 break;
 158         case SC_R_SATA_0:
 159                 boot_dev = SATA_BOOT;
 160                 break;
 161         case SC_R_USB_0:
 162         case SC_R_USB_1:
 163         case SC_R_USB_2:
 164                 boot_dev = USB_BOOT;
 165                 break;
 166         default:
 167                 break;
 168         }
 169
 170         return boot_dev;
 171 }
 172
 173 #ifdef CONFIG_SERIAL_TAG
 174 #define FUSE_UNIQUE_ID_WORD0 16
 175 #define FUSE_UNIQUE_ID_WORD1 17
 176 void get_board_serial(struct tag_serialnr *serialnr)
 177 {
 178         sc_err_t err;
 179         u32 val1 = 0, val2 = 0;
 180         u32 word1, word2;
 181
 182         if (!serialnr)
 183                 return;
 184
 185         word1 = FUSE_UNIQUE_ID_WORD0;
 186         word2 = FUSE_UNIQUE_ID_WORD1;
 187
 188         err = sc_misc_otp_fuse_read(-1, word1, &val1);
 189         if (err != SC_ERR_NONE) {
 190                 printf("%s fuse %d read error: %d\n", __func__, word1, err);
 191                 return;
 192         }
 193
 194         err = sc_misc_otp_fuse_read(-1, word2, &val2);
 195         if (err != SC_ERR_NONE) {
 196                 printf("%s fuse %d read error: %d\n", __func__, word2, err);
 197                 return;
 198         }
 199         serialnr->low = val1;
 200         serialnr->high = val2;
 201 }
 202 #endif /*CONFIG_SERIAL_TAG*/
 203
 204 #ifdef CONFIG_ENV_IS_IN_MMC
 205 __weak int board_mmc_get_env_dev(int devno)
 206 {
 207         return CONFIG_SYS_MMC_ENV_DEV;
 208 }
 209
 210 int mmc_get_env_dev(void)
 211 {
 212         sc_rsrc_t dev_rsrc;
 213         int devno;
 214
 215         sc_misc_get_boot_dev(-1, &dev_rsrc);
 216
 217         switch (dev_rsrc) {
 218         case SC_R_SDHC_0:
 219                 devno = 0;
 220                 break;
 221         case SC_R_SDHC_1:
 222                 devno = 1;
 223                 break;
 224         case SC_R_SDHC_2:
 225                 devno = 2;
 226                 break;
 227         default:
 228                 /* If not boot from sd/mmc, use default value */
 229                 return CONFIG_SYS_MMC_ENV_DEV;
 230         }
 231
 232         return board_mmc_get_env_dev(devno);
 233 }
 234 #endif
 235
 236 #define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */
 237
 238 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
 239                             sc_faddr_t *addr_end)
 240 {
 241         sc_faddr_t start, end;
 242         int ret;
 243         bool owned;
 244
 245         owned = sc_rm_is_memreg_owned(-1, mr);
 246         if (owned) {
 247                 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
 248                 if (ret) {
 249                         printf("Memreg get info failed, %d\n", ret);
 250                         return -EINVAL;
 251                 }
 252                 debug("0x%llx -- 0x%llx\n", start, end);
 253                 *addr_start = start;
 254                 *addr_end = end;
 255
 256                 return 0;
 257         }
 258
 259         return -EINVAL;
 260 }
 261
 262 phys_size_t get_effective_memsize(void)
 263 {
 264         sc_rm_mr_t mr;
 265         sc_faddr_t start, end, end1, start_aligned;
 266         int err;
 267
 268         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 269
 270         for (mr = 0; mr < 64; mr++) {
 271                 err = get_owned_memreg(mr, &start, &end);
 272                 if (!err) {
 273                         start_aligned = roundup(start, MEMSTART_ALIGNMENT);
 274                         /* Too small memory region, not use it */
 275                         if (start_aligned > end)
 276                                 continue;
 277
 278                         /* Find the memory region runs the U-Boot */
 279                         if (start >= PHYS_SDRAM_1 && start <= end1 &&
 280                             (start <= CONFIG_SYS_TEXT_BASE &&
 281                             end >= CONFIG_SYS_TEXT_BASE)) {
 282                                 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
 283                                     PHYS_SDRAM_1_SIZE))
 284                                         return (end - PHYS_SDRAM_1 + 1);
 285                                 else
 286                                         return PHYS_SDRAM_1_SIZE;
 287                         }
 288                 }
 289         }
 290
 291         return PHYS_SDRAM_1_SIZE;
 292 }
 293
 294 int dram_init(void)
 295 {
 296         sc_rm_mr_t mr;
 297         sc_faddr_t start, end, end1, end2;
 298         int err;
 299
 300         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 301         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 302         for (mr = 0; mr < 64; mr++) {
 303                 err = get_owned_memreg(mr, &start, &end);
 304                 if (!err) {
 305                         start = roundup(start, MEMSTART_ALIGNMENT);
 306                         /* Too small memory region, not use it */
 307                         if (start > end)
 308                                 continue;
 309
 310                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 311                                 if ((end + 1) <= end1)
 312                                         gd->ram_size += end - start + 1;
 313                                 else
 314                                         gd->ram_size += end1 - start;
 315                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 316                                 if ((end + 1) <= end2)
 317                                         gd->ram_size += end - start + 1;
 318                                 else
 319                                         gd->ram_size += end2 - start;
 320                         }
 321                 }
 322         }
 323
 324         /* If error, set to the default value */
 325         if (!gd->ram_size) {
 326                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 327                 gd->ram_size += PHYS_SDRAM_2_SIZE;
 328         }
 329         return 0;
 330 }
 331
 332 static void dram_bank_sort(int current_bank)
 333 {
 334         phys_addr_t start;
 335         phys_size_t size;
 336
 337         while (current_bank > 0) {
 338                 if (gd->bd->bi_dram[current_bank - 1].start >
 339                     gd->bd->bi_dram[current_bank].start) {
 340                         start = gd->bd->bi_dram[current_bank - 1].start;
 341                         size = gd->bd->bi_dram[current_bank - 1].size;
 342
 343                         gd->bd->bi_dram[current_bank - 1].start =
 344                                 gd->bd->bi_dram[current_bank].start;
 345                         gd->bd->bi_dram[current_bank - 1].size =
 346                                 gd->bd->bi_dram[current_bank].size;
 347
 348                         gd->bd->bi_dram[current_bank].start = start;
 349                         gd->bd->bi_dram[current_bank].size = size;
 350                 }
 351                 current_bank--;
 352         }
 353 }
 354
 355 int dram_init_banksize(void)
 356 {
 357         sc_rm_mr_t mr;
 358         sc_faddr_t start, end, end1, end2;
 359         int i = 0;
 360         int err;
 361
 362         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 363         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 364
 365         for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
 366                 err = get_owned_memreg(mr, &start, &end);
 367                 if (!err) {
 368                         start = roundup(start, MEMSTART_ALIGNMENT);
 369                         if (start > end) /* Small memory region, no use it */
 370                                 continue;
 371
 372                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 373                                 gd->bd->bi_dram[i].start = start;
 374
 375                                 if ((end + 1) <= end1)
 376                                         gd->bd->bi_dram[i].size =
 377                                                 end - start + 1;
 378                                 else
 379                                         gd->bd->bi_dram[i].size = end1 - start;
 380
 381                                 dram_bank_sort(i);
 382                                 i++;
 383                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 384                                 gd->bd->bi_dram[i].start = start;
 385
 386                                 if ((end + 1) <= end2)
 387                                         gd->bd->bi_dram[i].size =
 388                                                 end - start + 1;
 389                                 else
 390                                         gd->bd->bi_dram[i].size = end2 - start;
 391
 392                                 dram_bank_sort(i);
 393                                 i++;
 394                         }
 395                 }
 396         }
 397
 398         /* If error, set to the default value */
 399         if (!i) {
 400                 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 401                 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 402                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 403                 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 404         }
 405
 406         return 0;
 407 }
 408
 409 static u64 get_block_attrs(sc_faddr_t addr_start)
 410 {
 411         u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
 412                 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 413
 414         if ((addr_start >= PHYS_SDRAM_1 &&
 415              addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
 416             (addr_start >= PHYS_SDRAM_2 &&
 417              addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
 418                 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
 419
 420         return attr;
 421 }
 422
 423 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
 424 {
 425         sc_faddr_t end1, end2;
 426
 427         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 428         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 429
 430         if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
 431                 if ((addr_end + 1) > end1)
 432                         return end1 - addr_start;
 433         } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
 434                 if ((addr_end + 1) > end2)
 435                         return end2 - addr_start;
 436         }
 437
 438         return (addr_end - addr_start + 1);
 439 }
 440
 441 #define MAX_PTE_ENTRIES 512
 442 #define MAX_MEM_MAP_REGIONS 16
 443
 444 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
 445 struct mm_region *mem_map = imx8_mem_map;
 446
 447 void enable_caches(void)
 448 {
 449         sc_rm_mr_t mr;
 450         sc_faddr_t start, end;
 451         int err, i;
 452
 453         /* Create map for registers access from 0x1c000000 to 0x80000000*/
 454         imx8_mem_map[0].virt = 0x1c000000UL;
 455         imx8_mem_map[0].phys = 0x1c000000UL;
 456         imx8_mem_map[0].size = 0x64000000UL;
 457         imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 458                          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 459
 460         i = 1;
 461         for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
 462                 err = get_owned_memreg(mr, &start, &end);
 463                 if (!err) {
 464                         imx8_mem_map[i].virt = start;
 465                         imx8_mem_map[i].phys = start;
 466                         imx8_mem_map[i].size = get_block_size(start, end);
 467                         imx8_mem_map[i].attrs = get_block_attrs(start);
 468                         i++;
 469                 }
 470         }
 471
 472         if (i < MAX_MEM_MAP_REGIONS) {
 473                 imx8_mem_map[i].size = 0;
 474                 imx8_mem_map[i].attrs = 0;
 475         } else {
 476                 puts("Error, need more MEM MAP REGIONS reserved\n");
 477                 icache_enable();
 478                 return;
 479         }
 480
 481         for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
 482                 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
 483                       i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
 484                       imx8_mem_map[i].size, imx8_mem_map[i].attrs);
 485         }
 486
 487         icache_enable();
 488         dcache_enable();
 489 }
 490
 491 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 492 u64 get_page_table_size(void)
 493 {
 494         u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
 495         u64 size = 0;
 496
 497         /*
 498          * For each memory region, the max table size:
 499          * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
 500          */
 501         size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
 502
 503         /*
 504          * We need to duplicate our page table once to have an emergency pt to
 505          * resort to when splitting page tables later on
 506          */
 507         size *= 2;
 508
 509         /*
 510          * We may need to split page tables later on if dcache settings change,
 511          * so reserve up to 4 (random pick) page tables for that.
 512          */
 513         size += one_pt * 4;
 514
 515         return size;
 516 }
 517 #endif
 518
 519 #if defined(CONFIG_IMX8QM)
 520 #define FUSE_MAC0_WORD0 452
 521 #define FUSE_MAC0_WORD1 453
 522 #define FUSE_MAC1_WORD0 454
 523 #define FUSE_MAC1_WORD1 455
 524 #elif defined(CONFIG_IMX8QXP)
 525 #define FUSE_MAC0_WORD0 708
 526 #define FUSE_MAC0_WORD1 709
 527 #define FUSE_MAC1_WORD0 710
 528 #define FUSE_MAC1_WORD1 711
 529 #endif
 530
 531 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 532 {
 533         u32 word[2], val[2] = {};
 534         int i, ret;
 535
 536         if (dev_id == 0) {
 537                 word[0] = FUSE_MAC0_WORD0;
 538                 word[1] = FUSE_MAC0_WORD1;
 539         } else {
 540                 word[0] = FUSE_MAC1_WORD0;
 541                 word[1] = FUSE_MAC1_WORD1;
 542         }
 543
 544         for (i = 0; i < 2; i++) {
 545                 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
 546                 if (ret < 0)
 547                         goto err;
 548         }
 549
 550         mac[0] = val[0];
 551         mac[1] = val[0] >> 8;
 552         mac[2] = val[0] >> 16;
 553         mac[3] = val[0] >> 24;
 554         mac[4] = val[1];
 555         mac[5] = val[1] >> 8;
 556
 557         debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
 558               __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 559         return;
 560 err:
 561         printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
 562 }
 563
 564 u32 get_cpu_rev(void)
 565 {
 566         u32 id = 0, rev = 0;
 567         int ret;
 568
 569         ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
 570         if (ret)
 571                 return 0;
 572
 573         rev = (id >> 5)  & 0xf;
 574         id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */
 575
 576         return (id << 12) | rev;
 577 }
 578
 579 void board_boot_order(u32 *spl_boot_list)
 580 {
 581         spl_boot_list[0] = spl_boot_device();
 582
 583         if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
 584                 /* Check whether we own the flexspi0, if not, use NOR boot */
 585                 if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
 586                         spl_boot_list[0] = BOOT_DEVICE_NOR;
 587         }
 588 }
 589
 590 bool m4_parts_booted(void)
 591 {
 592         sc_rm_pt_t m4_parts[2];
 593         int err;
 594
 595         err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
 596         if (err) {
 597                 printf("%s get resource [%d] owner error: %d\n", __func__,
 598                        SC_R_M4_0_PID0, err);
 599                 return false;
 600         }
 601
 602         if (sc_pm_is_partition_started(-1, m4_parts[0]))
 603                 return true;
 604
 605         if (is_imx8qm()) {
 606                 err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
 607                 if (err) {
 608                         printf("%s get resource [%d] owner error: %d\n",
 609                                __func__, SC_R_M4_1_PID0, err);
 610                         return false;
 611                 }
 612
 613                 if (sc_pm_is_partition_started(-1, m4_parts[1]))
 614                         return true;
 615         }
 616
 617         return false;
 618 }