arch/arm/mach-imx/imx8/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <cpu.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <init.h>
  12 #include <dm/device-internal.h>
  13 #include <dm/lists.h>
  14 #include <dm/uclass.h>
  15 #include <errno.h>
  16 #include <thermal.h>
  17 #include <asm/arch/sci/sci.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch-imx/cpu.h>
  20 #include <asm/armv8/cpu.h>
  21 #include <asm/armv8/mmu.h>
  22 #include <asm/setup.h>
  23 #include <asm/mach-imx/boot_mode.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #define BT_PASSOVER_TAG 0x504F
  28 struct pass_over_info_t *get_pass_over_info(void)
  29 {
  30         struct pass_over_info_t *p =
  31                 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
  32
  33         if (p->barker != BT_PASSOVER_TAG ||
  34             p->len != sizeof(struct pass_over_info_t))
  35                 return NULL;
  36
  37         return p;
  38 }
  39
  40 int arch_cpu_init(void)
  41 {
  42 #ifdef CONFIG_SPL_BUILD
  43         struct pass_over_info_t *pass_over;
  44
  45         if (is_soc_rev(CHIP_REV_A)) {
  46                 pass_over = get_pass_over_info();
  47                 if (pass_over && pass_over->g_ap_mu == 0) {
  48                         /*
  49                          * When ap_mu is 0, means the U-Boot booted
  50                          * from first container
  51                          */
  52                         sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
  53                 }
  54         }
  55 #endif
  56
  57         return 0;
  58 }
  59
  60 int arch_cpu_init_dm(void)
  61 {
  62         struct udevice *devp;
  63         int node, ret;
  64
  65         node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
  66
  67         ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
  68         if (ret) {
  69                 printf("could not get scu %d\n", ret);
  70                 return ret;
  71         }
  72
  73         if (is_imx8qm()) {
  74                 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
  75                                                     SC_PM_PW_MODE_ON);
  76                 if (ret)
  77                         return ret;
  78         }
  79
  80         return 0;
  81 }
  82
  83 int print_bootinfo(void)
  84 {
  85         enum boot_device bt_dev = get_boot_device();
  86
  87         puts("Boot:  ");
  88         switch (bt_dev) {
  89         case SD1_BOOT:
  90                 puts("SD0\n");
  91                 break;
  92         case SD2_BOOT:
  93                 puts("SD1\n");
  94                 break;
  95         case SD3_BOOT:
  96                 puts("SD2\n");
  97                 break;
  98         case MMC1_BOOT:
  99                 puts("MMC0\n");
 100                 break;
 101         case MMC2_BOOT:
 102                 puts("MMC1\n");
 103                 break;
 104         case MMC3_BOOT:
 105                 puts("MMC2\n");
 106                 break;
 107         case FLEXSPI_BOOT:
 108                 puts("FLEXSPI\n");
 109                 break;
 110         case SATA_BOOT:
 111                 puts("SATA\n");
 112                 break;
 113         case NAND_BOOT:
 114                 puts("NAND\n");
 115                 break;
 116         case USB_BOOT:
 117                 puts("USB\n");
 118                 break;
 119         default:
 120                 printf("Unknown device %u\n", bt_dev);
 121                 break;
 122         }
 123
 124         return 0;
 125 }
 126
 127 enum boot_device get_boot_device(void)
 128 {
 129         enum boot_device boot_dev = SD1_BOOT;
 130
 131         sc_rsrc_t dev_rsrc;
 132
 133         sc_misc_get_boot_dev(-1, &dev_rsrc);
 134
 135         switch (dev_rsrc) {
 136         case SC_R_SDHC_0:
 137                 boot_dev = MMC1_BOOT;
 138                 break;
 139         case SC_R_SDHC_1:
 140                 boot_dev = SD2_BOOT;
 141                 break;
 142         case SC_R_SDHC_2:
 143                 boot_dev = SD3_BOOT;
 144                 break;
 145         case SC_R_NAND:
 146                 boot_dev = NAND_BOOT;
 147                 break;
 148         case SC_R_FSPI_0:
 149                 boot_dev = FLEXSPI_BOOT;
 150                 break;
 151         case SC_R_SATA_0:
 152                 boot_dev = SATA_BOOT;
 153                 break;
 154         case SC_R_USB_0:
 155         case SC_R_USB_1:
 156         case SC_R_USB_2:
 157                 boot_dev = USB_BOOT;
 158                 break;
 159         default:
 160                 break;
 161         }
 162
 163         return boot_dev;
 164 }
 165
 166 #ifdef CONFIG_SERIAL_TAG
 167 #define FUSE_UNIQUE_ID_WORD0 16
 168 #define FUSE_UNIQUE_ID_WORD1 17
 169 void get_board_serial(struct tag_serialnr *serialnr)
 170 {
 171         sc_err_t err;
 172         u32 val1 = 0, val2 = 0;
 173         u32 word1, word2;
 174
 175         if (!serialnr)
 176                 return;
 177
 178         word1 = FUSE_UNIQUE_ID_WORD0;
 179         word2 = FUSE_UNIQUE_ID_WORD1;
 180
 181         err = sc_misc_otp_fuse_read(-1, word1, &val1);
 182         if (err != SC_ERR_NONE) {
 183                 printf("%s fuse %d read error: %d\n", __func__, word1, err);
 184                 return;
 185         }
 186
 187         err = sc_misc_otp_fuse_read(-1, word2, &val2);
 188         if (err != SC_ERR_NONE) {
 189                 printf("%s fuse %d read error: %d\n", __func__, word2, err);
 190                 return;
 191         }
 192         serialnr->low = val1;
 193         serialnr->high = val2;
 194 }
 195 #endif /*CONFIG_SERIAL_TAG*/
 196
 197 #ifdef CONFIG_ENV_IS_IN_MMC
 198 __weak int board_mmc_get_env_dev(int devno)
 199 {
 200         return CONFIG_SYS_MMC_ENV_DEV;
 201 }
 202
 203 int mmc_get_env_dev(void)
 204 {
 205         sc_rsrc_t dev_rsrc;
 206         int devno;
 207
 208         sc_misc_get_boot_dev(-1, &dev_rsrc);
 209
 210         switch (dev_rsrc) {
 211         case SC_R_SDHC_0:
 212                 devno = 0;
 213                 break;
 214         case SC_R_SDHC_1:
 215                 devno = 1;
 216                 break;
 217         case SC_R_SDHC_2:
 218                 devno = 2;
 219                 break;
 220         default:
 221                 /* If not boot from sd/mmc, use default value */
 222                 return CONFIG_SYS_MMC_ENV_DEV;
 223         }
 224
 225         return board_mmc_get_env_dev(devno);
 226 }
 227 #endif
 228
 229 #define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */
 230
 231 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
 232                             sc_faddr_t *addr_end)
 233 {
 234         sc_faddr_t start, end;
 235         int ret;
 236         bool owned;
 237
 238         owned = sc_rm_is_memreg_owned(-1, mr);
 239         if (owned) {
 240                 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
 241                 if (ret) {
 242                         printf("Memreg get info failed, %d\n", ret);
 243                         return -EINVAL;
 244                 }
 245                 debug("0x%llx -- 0x%llx\n", start, end);
 246                 *addr_start = start;
 247                 *addr_end = end;
 248
 249                 return 0;
 250         }
 251
 252         return -EINVAL;
 253 }
 254
 255 phys_size_t get_effective_memsize(void)
 256 {
 257         sc_rm_mr_t mr;
 258         sc_faddr_t start, end, end1, start_aligned;
 259         int err;
 260
 261         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 262
 263         for (mr = 0; mr < 64; mr++) {
 264                 err = get_owned_memreg(mr, &start, &end);
 265                 if (!err) {
 266                         start_aligned = roundup(start, MEMSTART_ALIGNMENT);
 267                         /* Too small memory region, not use it */
 268                         if (start_aligned > end)
 269                                 continue;
 270
 271                         /* Find the memory region runs the U-Boot */
 272                         if (start >= PHYS_SDRAM_1 && start <= end1 &&
 273                             (start <= CONFIG_SYS_TEXT_BASE &&
 274                             end >= CONFIG_SYS_TEXT_BASE)) {
 275                                 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
 276                                     PHYS_SDRAM_1_SIZE))
 277                                         return (end - PHYS_SDRAM_1 + 1);
 278                                 else
 279                                         return PHYS_SDRAM_1_SIZE;
 280                         }
 281                 }
 282         }
 283
 284         return PHYS_SDRAM_1_SIZE;
 285 }
 286
 287 int dram_init(void)
 288 {
 289         sc_rm_mr_t mr;
 290         sc_faddr_t start, end, end1, end2;
 291         int err;
 292
 293         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 294         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 295         for (mr = 0; mr < 64; mr++) {
 296                 err = get_owned_memreg(mr, &start, &end);
 297                 if (!err) {
 298                         start = roundup(start, MEMSTART_ALIGNMENT);
 299                         /* Too small memory region, not use it */
 300                         if (start > end)
 301                                 continue;
 302
 303                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 304                                 if ((end + 1) <= end1)
 305                                         gd->ram_size += end - start + 1;
 306                                 else
 307                                         gd->ram_size += end1 - start;
 308                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 309                                 if ((end + 1) <= end2)
 310                                         gd->ram_size += end - start + 1;
 311                                 else
 312                                         gd->ram_size += end2 - start;
 313                         }
 314                 }
 315         }
 316
 317         /* If error, set to the default value */
 318         if (!gd->ram_size) {
 319                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 320                 gd->ram_size += PHYS_SDRAM_2_SIZE;
 321         }
 322         return 0;
 323 }
 324
 325 static void dram_bank_sort(int current_bank)
 326 {
 327         phys_addr_t start;
 328         phys_size_t size;
 329
 330         while (current_bank > 0) {
 331                 if (gd->bd->bi_dram[current_bank - 1].start >
 332                     gd->bd->bi_dram[current_bank].start) {
 333                         start = gd->bd->bi_dram[current_bank - 1].start;
 334                         size = gd->bd->bi_dram[current_bank - 1].size;
 335
 336                         gd->bd->bi_dram[current_bank - 1].start =
 337                                 gd->bd->bi_dram[current_bank].start;
 338                         gd->bd->bi_dram[current_bank - 1].size =
 339                                 gd->bd->bi_dram[current_bank].size;
 340
 341                         gd->bd->bi_dram[current_bank].start = start;
 342                         gd->bd->bi_dram[current_bank].size = size;
 343                 }
 344                 current_bank--;
 345         }
 346 }
 347
 348 int dram_init_banksize(void)
 349 {
 350         sc_rm_mr_t mr;
 351         sc_faddr_t start, end, end1, end2;
 352         int i = 0;
 353         int err;
 354
 355         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 356         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 357
 358         for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
 359                 err = get_owned_memreg(mr, &start, &end);
 360                 if (!err) {
 361                         start = roundup(start, MEMSTART_ALIGNMENT);
 362                         if (start > end) /* Small memory region, no use it */
 363                                 continue;
 364
 365                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 366                                 gd->bd->bi_dram[i].start = start;
 367
 368                                 if ((end + 1) <= end1)
 369                                         gd->bd->bi_dram[i].size =
 370                                                 end - start + 1;
 371                                 else
 372                                         gd->bd->bi_dram[i].size = end1 - start;
 373
 374                                 dram_bank_sort(i);
 375                                 i++;
 376                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 377                                 gd->bd->bi_dram[i].start = start;
 378
 379                                 if ((end + 1) <= end2)
 380                                         gd->bd->bi_dram[i].size =
 381                                                 end - start + 1;
 382                                 else
 383                                         gd->bd->bi_dram[i].size = end2 - start;
 384
 385                                 dram_bank_sort(i);
 386                                 i++;
 387                         }
 388                 }
 389         }
 390
 391         /* If error, set to the default value */
 392         if (!i) {
 393                 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 394                 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 395                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 396                 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 397         }
 398
 399         return 0;
 400 }
 401
 402 static u64 get_block_attrs(sc_faddr_t addr_start)
 403 {
 404         u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
 405                 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 406
 407         if ((addr_start >= PHYS_SDRAM_1 &&
 408              addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
 409             (addr_start >= PHYS_SDRAM_2 &&
 410              addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
 411                 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
 412
 413         return attr;
 414 }
 415
 416 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
 417 {
 418         sc_faddr_t end1, end2;
 419
 420         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 421         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 422
 423         if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
 424                 if ((addr_end + 1) > end1)
 425                         return end1 - addr_start;
 426         } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
 427                 if ((addr_end + 1) > end2)
 428                         return end2 - addr_start;
 429         }
 430
 431         return (addr_end - addr_start + 1);
 432 }
 433
 434 #define MAX_PTE_ENTRIES 512
 435 #define MAX_MEM_MAP_REGIONS 16
 436
 437 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
 438 struct mm_region *mem_map = imx8_mem_map;
 439
 440 void enable_caches(void)
 441 {
 442         sc_rm_mr_t mr;
 443         sc_faddr_t start, end;
 444         int err, i;
 445
 446         /* Create map for registers access from 0x1c000000 to 0x80000000*/
 447         imx8_mem_map[0].virt = 0x1c000000UL;
 448         imx8_mem_map[0].phys = 0x1c000000UL;
 449         imx8_mem_map[0].size = 0x64000000UL;
 450         imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 451                          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 452
 453         i = 1;
 454         for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
 455                 err = get_owned_memreg(mr, &start, &end);
 456                 if (!err) {
 457                         imx8_mem_map[i].virt = start;
 458                         imx8_mem_map[i].phys = start;
 459                         imx8_mem_map[i].size = get_block_size(start, end);
 460                         imx8_mem_map[i].attrs = get_block_attrs(start);
 461                         i++;
 462                 }
 463         }
 464
 465         if (i < MAX_MEM_MAP_REGIONS) {
 466                 imx8_mem_map[i].size = 0;
 467                 imx8_mem_map[i].attrs = 0;
 468         } else {
 469                 puts("Error, need more MEM MAP REGIONS reserved\n");
 470                 icache_enable();
 471                 return;
 472         }
 473
 474         for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
 475                 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
 476                       i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
 477                       imx8_mem_map[i].size, imx8_mem_map[i].attrs);
 478         }
 479
 480         icache_enable();
 481         dcache_enable();
 482 }
 483
 484 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 485 u64 get_page_table_size(void)
 486 {
 487         u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
 488         u64 size = 0;
 489
 490         /*
 491          * For each memory region, the max table size:
 492          * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
 493          */
 494         size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
 495
 496         /*
 497          * We need to duplicate our page table once to have an emergency pt to
 498          * resort to when splitting page tables later on
 499          */
 500         size *= 2;
 501
 502         /*
 503          * We may need to split page tables later on if dcache settings change,
 504          * so reserve up to 4 (random pick) page tables for that.
 505          */
 506         size += one_pt * 4;
 507
 508         return size;
 509 }
 510 #endif
 511
 512 #if defined(CONFIG_IMX8QM)
 513 #define FUSE_MAC0_WORD0 452
 514 #define FUSE_MAC0_WORD1 453
 515 #define FUSE_MAC1_WORD0 454
 516 #define FUSE_MAC1_WORD1 455
 517 #elif defined(CONFIG_IMX8QXP)
 518 #define FUSE_MAC0_WORD0 708
 519 #define FUSE_MAC0_WORD1 709
 520 #define FUSE_MAC1_WORD0 710
 521 #define FUSE_MAC1_WORD1 711
 522 #endif
 523
 524 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 525 {
 526         u32 word[2], val[2] = {};
 527         int i, ret;
 528
 529         if (dev_id == 0) {
 530                 word[0] = FUSE_MAC0_WORD0;
 531                 word[1] = FUSE_MAC0_WORD1;
 532         } else {
 533                 word[0] = FUSE_MAC1_WORD0;
 534                 word[1] = FUSE_MAC1_WORD1;
 535         }
 536
 537         for (i = 0; i < 2; i++) {
 538                 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
 539                 if (ret < 0)
 540                         goto err;
 541         }
 542
 543         mac[0] = val[0];
 544         mac[1] = val[0] >> 8;
 545         mac[2] = val[0] >> 16;
 546         mac[3] = val[0] >> 24;
 547         mac[4] = val[1];
 548         mac[5] = val[1] >> 8;
 549
 550         debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
 551               __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 552         return;
 553 err:
 554         printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
 555 }
 556
 557 u32 get_cpu_rev(void)
 558 {
 559         u32 id = 0, rev = 0;
 560         int ret;
 561
 562         ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
 563         if (ret)
 564                 return 0;
 565
 566         rev = (id >> 5)  & 0xf;
 567         id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */
 568
 569         return (id << 12) | rev;
 570 }