arch/arm/mach-imx/imx8/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <cpu.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <init.h>
  12 #include <dm/device-internal.h>
  13 #include <dm/lists.h>
  14 #include <dm/uclass.h>
  15 #include <errno.h>
  16 #include <thermal.h>
  17 #include <asm/arch/sci/sci.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch-imx/cpu.h>
  20 #include <asm/armv8/cpu.h>
  21 #include <asm/armv8/mmu.h>
  22 #include <asm/mach-imx/boot_mode.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define BT_PASSOVER_TAG 0x504F
  27 struct pass_over_info_t *get_pass_over_info(void)
  28 {
  29         struct pass_over_info_t *p =
  30                 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
  31
  32         if (p->barker != BT_PASSOVER_TAG ||
  33             p->len != sizeof(struct pass_over_info_t))
  34                 return NULL;
  35
  36         return p;
  37 }
  38
  39 int arch_cpu_init(void)
  40 {
  41 #ifdef CONFIG_SPL_BUILD
  42         struct pass_over_info_t *pass_over;
  43
  44         if (is_soc_rev(CHIP_REV_A)) {
  45                 pass_over = get_pass_over_info();
  46                 if (pass_over && pass_over->g_ap_mu == 0) {
  47                         /*
  48                          * When ap_mu is 0, means the U-Boot booted
  49                          * from first container
  50                          */
  51                         sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
  52                 }
  53         }
  54 #endif
  55
  56         return 0;
  57 }
  58
  59 int arch_cpu_init_dm(void)
  60 {
  61         struct udevice *devp;
  62         int node, ret;
  63
  64         node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
  65
  66         ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
  67         if (ret) {
  68                 printf("could not get scu %d\n", ret);
  69                 return ret;
  70         }
  71
  72         if (is_imx8qm()) {
  73                 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
  74                                                     SC_PM_PW_MODE_ON);
  75                 if (ret)
  76                         return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 int print_bootinfo(void)
  83 {
  84         enum boot_device bt_dev = get_boot_device();
  85
  86         puts("Boot:  ");
  87         switch (bt_dev) {
  88         case SD1_BOOT:
  89                 puts("SD0\n");
  90                 break;
  91         case SD2_BOOT:
  92                 puts("SD1\n");
  93                 break;
  94         case SD3_BOOT:
  95                 puts("SD2\n");
  96                 break;
  97         case MMC1_BOOT:
  98                 puts("MMC0\n");
  99                 break;
 100         case MMC2_BOOT:
 101                 puts("MMC1\n");
 102                 break;
 103         case MMC3_BOOT:
 104                 puts("MMC2\n");
 105                 break;
 106         case FLEXSPI_BOOT:
 107                 puts("FLEXSPI\n");
 108                 break;
 109         case SATA_BOOT:
 110                 puts("SATA\n");
 111                 break;
 112         case NAND_BOOT:
 113                 puts("NAND\n");
 114                 break;
 115         case USB_BOOT:
 116                 puts("USB\n");
 117                 break;
 118         default:
 119                 printf("Unknown device %u\n", bt_dev);
 120                 break;
 121         }
 122
 123         return 0;
 124 }
 125
 126 enum boot_device get_boot_device(void)
 127 {
 128         enum boot_device boot_dev = SD1_BOOT;
 129
 130         sc_rsrc_t dev_rsrc;
 131
 132         sc_misc_get_boot_dev(-1, &dev_rsrc);
 133
 134         switch (dev_rsrc) {
 135         case SC_R_SDHC_0:
 136                 boot_dev = MMC1_BOOT;
 137                 break;
 138         case SC_R_SDHC_1:
 139                 boot_dev = SD2_BOOT;
 140                 break;
 141         case SC_R_SDHC_2:
 142                 boot_dev = SD3_BOOT;
 143                 break;
 144         case SC_R_NAND:
 145                 boot_dev = NAND_BOOT;
 146                 break;
 147         case SC_R_FSPI_0:
 148                 boot_dev = FLEXSPI_BOOT;
 149                 break;
 150         case SC_R_SATA_0:
 151                 boot_dev = SATA_BOOT;
 152                 break;
 153         case SC_R_USB_0:
 154         case SC_R_USB_1:
 155         case SC_R_USB_2:
 156                 boot_dev = USB_BOOT;
 157                 break;
 158         default:
 159                 break;
 160         }
 161
 162         return boot_dev;
 163 }
 164
 165 #ifdef CONFIG_ENV_IS_IN_MMC
 166 __weak int board_mmc_get_env_dev(int devno)
 167 {
 168         return CONFIG_SYS_MMC_ENV_DEV;
 169 }
 170
 171 int mmc_get_env_dev(void)
 172 {
 173         sc_rsrc_t dev_rsrc;
 174         int devno;
 175
 176         sc_misc_get_boot_dev(-1, &dev_rsrc);
 177
 178         switch (dev_rsrc) {
 179         case SC_R_SDHC_0:
 180                 devno = 0;
 181                 break;
 182         case SC_R_SDHC_1:
 183                 devno = 1;
 184                 break;
 185         case SC_R_SDHC_2:
 186                 devno = 2;
 187                 break;
 188         default:
 189                 /* If not boot from sd/mmc, use default value */
 190                 return CONFIG_SYS_MMC_ENV_DEV;
 191         }
 192
 193         return board_mmc_get_env_dev(devno);
 194 }
 195 #endif
 196
 197 #define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */
 198
 199 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
 200                             sc_faddr_t *addr_end)
 201 {
 202         sc_faddr_t start, end;
 203         int ret;
 204         bool owned;
 205
 206         owned = sc_rm_is_memreg_owned(-1, mr);
 207         if (owned) {
 208                 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
 209                 if (ret) {
 210                         printf("Memreg get info failed, %d\n", ret);
 211                         return -EINVAL;
 212                 }
 213                 debug("0x%llx -- 0x%llx\n", start, end);
 214                 *addr_start = start;
 215                 *addr_end = end;
 216
 217                 return 0;
 218         }
 219
 220         return -EINVAL;
 221 }
 222
 223 phys_size_t get_effective_memsize(void)
 224 {
 225         sc_rm_mr_t mr;
 226         sc_faddr_t start, end, end1, start_aligned;
 227         int err;
 228
 229         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 230
 231         for (mr = 0; mr < 64; mr++) {
 232                 err = get_owned_memreg(mr, &start, &end);
 233                 if (!err) {
 234                         start_aligned = roundup(start, MEMSTART_ALIGNMENT);
 235                         /* Too small memory region, not use it */
 236                         if (start_aligned > end)
 237                                 continue;
 238
 239                         /* Find the memory region runs the U-Boot */
 240                         if (start >= PHYS_SDRAM_1 && start <= end1 &&
 241                             (start <= CONFIG_SYS_TEXT_BASE &&
 242                             end >= CONFIG_SYS_TEXT_BASE)) {
 243                                 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
 244                                     PHYS_SDRAM_1_SIZE))
 245                                         return (end - PHYS_SDRAM_1 + 1);
 246                                 else
 247                                         return PHYS_SDRAM_1_SIZE;
 248                         }
 249                 }
 250         }
 251
 252         return PHYS_SDRAM_1_SIZE;
 253 }
 254
 255 int dram_init(void)
 256 {
 257         sc_rm_mr_t mr;
 258         sc_faddr_t start, end, end1, end2;
 259         int err;
 260
 261         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 262         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 263         for (mr = 0; mr < 64; mr++) {
 264                 err = get_owned_memreg(mr, &start, &end);
 265                 if (!err) {
 266                         start = roundup(start, MEMSTART_ALIGNMENT);
 267                         /* Too small memory region, not use it */
 268                         if (start > end)
 269                                 continue;
 270
 271                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 272                                 if ((end + 1) <= end1)
 273                                         gd->ram_size += end - start + 1;
 274                                 else
 275                                         gd->ram_size += end1 - start;
 276                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 277                                 if ((end + 1) <= end2)
 278                                         gd->ram_size += end - start + 1;
 279                                 else
 280                                         gd->ram_size += end2 - start;
 281                         }
 282                 }
 283         }
 284
 285         /* If error, set to the default value */
 286         if (!gd->ram_size) {
 287                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 288                 gd->ram_size += PHYS_SDRAM_2_SIZE;
 289         }
 290         return 0;
 291 }
 292
 293 static void dram_bank_sort(int current_bank)
 294 {
 295         phys_addr_t start;
 296         phys_size_t size;
 297
 298         while (current_bank > 0) {
 299                 if (gd->bd->bi_dram[current_bank - 1].start >
 300                     gd->bd->bi_dram[current_bank].start) {
 301                         start = gd->bd->bi_dram[current_bank - 1].start;
 302                         size = gd->bd->bi_dram[current_bank - 1].size;
 303
 304                         gd->bd->bi_dram[current_bank - 1].start =
 305                                 gd->bd->bi_dram[current_bank].start;
 306                         gd->bd->bi_dram[current_bank - 1].size =
 307                                 gd->bd->bi_dram[current_bank].size;
 308
 309                         gd->bd->bi_dram[current_bank].start = start;
 310                         gd->bd->bi_dram[current_bank].size = size;
 311                 }
 312                 current_bank--;
 313         }
 314 }
 315
 316 int dram_init_banksize(void)
 317 {
 318         sc_rm_mr_t mr;
 319         sc_faddr_t start, end, end1, end2;
 320         int i = 0;
 321         int err;
 322
 323         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 324         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 325
 326         for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
 327                 err = get_owned_memreg(mr, &start, &end);
 328                 if (!err) {
 329                         start = roundup(start, MEMSTART_ALIGNMENT);
 330                         if (start > end) /* Small memory region, no use it */
 331                                 continue;
 332
 333                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 334                                 gd->bd->bi_dram[i].start = start;
 335
 336                                 if ((end + 1) <= end1)
 337                                         gd->bd->bi_dram[i].size =
 338                                                 end - start + 1;
 339                                 else
 340                                         gd->bd->bi_dram[i].size = end1 - start;
 341
 342                                 dram_bank_sort(i);
 343                                 i++;
 344                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 345                                 gd->bd->bi_dram[i].start = start;
 346
 347                                 if ((end + 1) <= end2)
 348                                         gd->bd->bi_dram[i].size =
 349                                                 end - start + 1;
 350                                 else
 351                                         gd->bd->bi_dram[i].size = end2 - start;
 352
 353                                 dram_bank_sort(i);
 354                                 i++;
 355                         }
 356                 }
 357         }
 358
 359         /* If error, set to the default value */
 360         if (!i) {
 361                 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 362                 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 363                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 364                 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 365         }
 366
 367         return 0;
 368 }
 369
 370 static u64 get_block_attrs(sc_faddr_t addr_start)
 371 {
 372         u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
 373                 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 374
 375         if ((addr_start >= PHYS_SDRAM_1 &&
 376              addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
 377             (addr_start >= PHYS_SDRAM_2 &&
 378              addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
 379                 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
 380
 381         return attr;
 382 }
 383
 384 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
 385 {
 386         sc_faddr_t end1, end2;
 387
 388         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 389         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 390
 391         if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
 392                 if ((addr_end + 1) > end1)
 393                         return end1 - addr_start;
 394         } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
 395                 if ((addr_end + 1) > end2)
 396                         return end2 - addr_start;
 397         }
 398
 399         return (addr_end - addr_start + 1);
 400 }
 401
 402 #define MAX_PTE_ENTRIES 512
 403 #define MAX_MEM_MAP_REGIONS 16
 404
 405 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
 406 struct mm_region *mem_map = imx8_mem_map;
 407
 408 void enable_caches(void)
 409 {
 410         sc_rm_mr_t mr;
 411         sc_faddr_t start, end;
 412         int err, i;
 413
 414         /* Create map for registers access from 0x1c000000 to 0x80000000*/
 415         imx8_mem_map[0].virt = 0x1c000000UL;
 416         imx8_mem_map[0].phys = 0x1c000000UL;
 417         imx8_mem_map[0].size = 0x64000000UL;
 418         imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 419                          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 420
 421         i = 1;
 422         for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
 423                 err = get_owned_memreg(mr, &start, &end);
 424                 if (!err) {
 425                         imx8_mem_map[i].virt = start;
 426                         imx8_mem_map[i].phys = start;
 427                         imx8_mem_map[i].size = get_block_size(start, end);
 428                         imx8_mem_map[i].attrs = get_block_attrs(start);
 429                         i++;
 430                 }
 431         }
 432
 433         if (i < MAX_MEM_MAP_REGIONS) {
 434                 imx8_mem_map[i].size = 0;
 435                 imx8_mem_map[i].attrs = 0;
 436         } else {
 437                 puts("Error, need more MEM MAP REGIONS reserved\n");
 438                 icache_enable();
 439                 return;
 440         }
 441
 442         for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
 443                 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
 444                       i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
 445                       imx8_mem_map[i].size, imx8_mem_map[i].attrs);
 446         }
 447
 448         icache_enable();
 449         dcache_enable();
 450 }
 451
 452 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 453 u64 get_page_table_size(void)
 454 {
 455         u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
 456         u64 size = 0;
 457
 458         /*
 459          * For each memory region, the max table size:
 460          * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
 461          */
 462         size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
 463
 464         /*
 465          * We need to duplicate our page table once to have an emergency pt to
 466          * resort to when splitting page tables later on
 467          */
 468         size *= 2;
 469
 470         /*
 471          * We may need to split page tables later on if dcache settings change,
 472          * so reserve up to 4 (random pick) page tables for that.
 473          */
 474         size += one_pt * 4;
 475
 476         return size;
 477 }
 478 #endif
 479
 480 #if defined(CONFIG_IMX8QM)
 481 #define FUSE_MAC0_WORD0 452
 482 #define FUSE_MAC0_WORD1 453
 483 #define FUSE_MAC1_WORD0 454
 484 #define FUSE_MAC1_WORD1 455
 485 #elif defined(CONFIG_IMX8QXP)
 486 #define FUSE_MAC0_WORD0 708
 487 #define FUSE_MAC0_WORD1 709
 488 #define FUSE_MAC1_WORD0 710
 489 #define FUSE_MAC1_WORD1 711
 490 #endif
 491
 492 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 493 {
 494         u32 word[2], val[2] = {};
 495         int i, ret;
 496
 497         if (dev_id == 0) {
 498                 word[0] = FUSE_MAC0_WORD0;
 499                 word[1] = FUSE_MAC0_WORD1;
 500         } else {
 501                 word[0] = FUSE_MAC1_WORD0;
 502                 word[1] = FUSE_MAC1_WORD1;
 503         }
 504
 505         for (i = 0; i < 2; i++) {
 506                 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
 507                 if (ret < 0)
 508                         goto err;
 509         }
 510
 511         mac[0] = val[0];
 512         mac[1] = val[0] >> 8;
 513         mac[2] = val[0] >> 16;
 514         mac[3] = val[0] >> 24;
 515         mac[4] = val[1];
 516         mac[5] = val[1] >> 8;
 517
 518         debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
 519               __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 520         return;
 521 err:
 522         printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
 523 }
 524
 525 u32 get_cpu_rev(void)
 526 {
 527         u32 id = 0, rev = 0;
 528         int ret;
 529
 530         ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
 531         if (ret)
 532                 return 0;
 533
 534         rev = (id >> 5)  & 0xf;
 535         id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */
 536
 537         return (id << 12) | rev;
 538 }