arch/arm/mach-imx/imx8/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <cpu.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <init.h>
  12 #include <dm/device-internal.h>
  13 #include <dm/lists.h>
  14 #include <dm/uclass.h>
  15 #include <errno.h>
  16 #include <spl.h>
  17 #include <thermal.h>
  18 #include <asm/arch/sci/sci.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch-imx/cpu.h>
  21 #include <asm/armv8/cpu.h>
  22 #include <asm/armv8/mmu.h>
  23 #include <asm/setup.h>
  24 #include <asm/mach-imx/boot_mode.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define BT_PASSOVER_TAG 0x504F
  29 struct pass_over_info_t *get_pass_over_info(void)
  30 {
  31         struct pass_over_info_t *p =
  32                 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
  33
  34         if (p->barker != BT_PASSOVER_TAG ||
  35             p->len != sizeof(struct pass_over_info_t))
  36                 return NULL;
  37
  38         return p;
  39 }
  40
  41 int arch_cpu_init(void)
  42 {
  43 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
  44         spl_save_restore_data();
  45 #endif
  46
  47 #ifdef CONFIG_SPL_BUILD
  48         struct pass_over_info_t *pass_over;
  49
  50         if (is_soc_rev(CHIP_REV_A)) {
  51                 pass_over = get_pass_over_info();
  52                 if (pass_over && pass_over->g_ap_mu == 0) {
  53                         /*
  54                          * When ap_mu is 0, means the U-Boot booted
  55                          * from first container
  56                          */
  57                         sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
  58                 }
  59         }
  60 #endif
  61
  62         return 0;
  63 }
  64
  65 int arch_cpu_init_dm(void)
  66 {
  67         struct udevice *devp;
  68         int node, ret;
  69
  70         node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
  71
  72         ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
  73         if (ret) {
  74                 printf("could not get scu %d\n", ret);
  75                 return ret;
  76         }
  77
  78         if (is_imx8qm()) {
  79                 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
  80                                                     SC_PM_PW_MODE_ON);
  81                 if (ret)
  82                         return ret;
  83         }
  84
  85         return 0;
  86 }
  87
  88 int print_bootinfo(void)
  89 {
  90         enum boot_device bt_dev = get_boot_device();
  91
  92         puts("Boot:  ");
  93         switch (bt_dev) {
  94         case SD1_BOOT:
  95                 puts("SD0\n");
  96                 break;
  97         case SD2_BOOT:
  98                 puts("SD1\n");
  99                 break;
 100         case SD3_BOOT:
 101                 puts("SD2\n");
 102                 break;
 103         case MMC1_BOOT:
 104                 puts("MMC0\n");
 105                 break;
 106         case MMC2_BOOT:
 107                 puts("MMC1\n");
 108                 break;
 109         case MMC3_BOOT:
 110                 puts("MMC2\n");
 111                 break;
 112         case FLEXSPI_BOOT:
 113                 puts("FLEXSPI\n");
 114                 break;
 115         case SATA_BOOT:
 116                 puts("SATA\n");
 117                 break;
 118         case NAND_BOOT:
 119                 puts("NAND\n");
 120                 break;
 121         case USB_BOOT:
 122                 puts("USB\n");
 123                 break;
 124         default:
 125                 printf("Unknown device %u\n", bt_dev);
 126                 break;
 127         }
 128
 129         return 0;
 130 }
 131
 132 enum boot_device get_boot_device(void)
 133 {
 134         enum boot_device boot_dev = SD1_BOOT;
 135
 136         sc_rsrc_t dev_rsrc;
 137
 138         sc_misc_get_boot_dev(-1, &dev_rsrc);
 139
 140         switch (dev_rsrc) {
 141         case SC_R_SDHC_0:
 142                 boot_dev = MMC1_BOOT;
 143                 break;
 144         case SC_R_SDHC_1:
 145                 boot_dev = SD2_BOOT;
 146                 break;
 147         case SC_R_SDHC_2:
 148                 boot_dev = SD3_BOOT;
 149                 break;
 150         case SC_R_NAND:
 151                 boot_dev = NAND_BOOT;
 152                 break;
 153         case SC_R_FSPI_0:
 154                 boot_dev = FLEXSPI_BOOT;
 155                 break;
 156         case SC_R_SATA_0:
 157                 boot_dev = SATA_BOOT;
 158                 break;
 159         case SC_R_USB_0:
 160         case SC_R_USB_1:
 161         case SC_R_USB_2:
 162                 boot_dev = USB_BOOT;
 163                 break;
 164         default:
 165                 break;
 166         }
 167
 168         return boot_dev;
 169 }
 170
 171 #ifdef CONFIG_SERIAL_TAG
 172 #define FUSE_UNIQUE_ID_WORD0 16
 173 #define FUSE_UNIQUE_ID_WORD1 17
 174 void get_board_serial(struct tag_serialnr *serialnr)
 175 {
 176         sc_err_t err;
 177         u32 val1 = 0, val2 = 0;
 178         u32 word1, word2;
 179
 180         if (!serialnr)
 181                 return;
 182
 183         word1 = FUSE_UNIQUE_ID_WORD0;
 184         word2 = FUSE_UNIQUE_ID_WORD1;
 185
 186         err = sc_misc_otp_fuse_read(-1, word1, &val1);
 187         if (err != SC_ERR_NONE) {
 188                 printf("%s fuse %d read error: %d\n", __func__, word1, err);
 189                 return;
 190         }
 191
 192         err = sc_misc_otp_fuse_read(-1, word2, &val2);
 193         if (err != SC_ERR_NONE) {
 194                 printf("%s fuse %d read error: %d\n", __func__, word2, err);
 195                 return;
 196         }
 197         serialnr->low = val1;
 198         serialnr->high = val2;
 199 }
 200 #endif /*CONFIG_SERIAL_TAG*/
 201
 202 #ifdef CONFIG_ENV_IS_IN_MMC
 203 __weak int board_mmc_get_env_dev(int devno)
 204 {
 205         return CONFIG_SYS_MMC_ENV_DEV;
 206 }
 207
 208 int mmc_get_env_dev(void)
 209 {
 210         sc_rsrc_t dev_rsrc;
 211         int devno;
 212
 213         sc_misc_get_boot_dev(-1, &dev_rsrc);
 214
 215         switch (dev_rsrc) {
 216         case SC_R_SDHC_0:
 217                 devno = 0;
 218                 break;
 219         case SC_R_SDHC_1:
 220                 devno = 1;
 221                 break;
 222         case SC_R_SDHC_2:
 223                 devno = 2;
 224                 break;
 225         default:
 226                 /* If not boot from sd/mmc, use default value */
 227                 return CONFIG_SYS_MMC_ENV_DEV;
 228         }
 229
 230         return board_mmc_get_env_dev(devno);
 231 }
 232 #endif
 233
 234 #define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */
 235
 236 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
 237                             sc_faddr_t *addr_end)
 238 {
 239         sc_faddr_t start, end;
 240         int ret;
 241         bool owned;
 242
 243         owned = sc_rm_is_memreg_owned(-1, mr);
 244         if (owned) {
 245                 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
 246                 if (ret) {
 247                         printf("Memreg get info failed, %d\n", ret);
 248                         return -EINVAL;
 249                 }
 250                 debug("0x%llx -- 0x%llx\n", start, end);
 251                 *addr_start = start;
 252                 *addr_end = end;
 253
 254                 return 0;
 255         }
 256
 257         return -EINVAL;
 258 }
 259
 260 phys_size_t get_effective_memsize(void)
 261 {
 262         sc_rm_mr_t mr;
 263         sc_faddr_t start, end, end1, start_aligned;
 264         int err;
 265
 266         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 267
 268         for (mr = 0; mr < 64; mr++) {
 269                 err = get_owned_memreg(mr, &start, &end);
 270                 if (!err) {
 271                         start_aligned = roundup(start, MEMSTART_ALIGNMENT);
 272                         /* Too small memory region, not use it */
 273                         if (start_aligned > end)
 274                                 continue;
 275
 276                         /* Find the memory region runs the U-Boot */
 277                         if (start >= PHYS_SDRAM_1 && start <= end1 &&
 278                             (start <= CONFIG_SYS_TEXT_BASE &&
 279                             end >= CONFIG_SYS_TEXT_BASE)) {
 280                                 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
 281                                     PHYS_SDRAM_1_SIZE))
 282                                         return (end - PHYS_SDRAM_1 + 1);
 283                                 else
 284                                         return PHYS_SDRAM_1_SIZE;
 285                         }
 286                 }
 287         }
 288
 289         return PHYS_SDRAM_1_SIZE;
 290 }
 291
 292 int dram_init(void)
 293 {
 294         sc_rm_mr_t mr;
 295         sc_faddr_t start, end, end1, end2;
 296         int err;
 297
 298         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 299         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 300         for (mr = 0; mr < 64; mr++) {
 301                 err = get_owned_memreg(mr, &start, &end);
 302                 if (!err) {
 303                         start = roundup(start, MEMSTART_ALIGNMENT);
 304                         /* Too small memory region, not use it */
 305                         if (start > end)
 306                                 continue;
 307
 308                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 309                                 if ((end + 1) <= end1)
 310                                         gd->ram_size += end - start + 1;
 311                                 else
 312                                         gd->ram_size += end1 - start;
 313                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 314                                 if ((end + 1) <= end2)
 315                                         gd->ram_size += end - start + 1;
 316                                 else
 317                                         gd->ram_size += end2 - start;
 318                         }
 319                 }
 320         }
 321
 322         /* If error, set to the default value */
 323         if (!gd->ram_size) {
 324                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 325                 gd->ram_size += PHYS_SDRAM_2_SIZE;
 326         }
 327         return 0;
 328 }
 329
 330 static void dram_bank_sort(int current_bank)
 331 {
 332         phys_addr_t start;
 333         phys_size_t size;
 334
 335         while (current_bank > 0) {
 336                 if (gd->bd->bi_dram[current_bank - 1].start >
 337                     gd->bd->bi_dram[current_bank].start) {
 338                         start = gd->bd->bi_dram[current_bank - 1].start;
 339                         size = gd->bd->bi_dram[current_bank - 1].size;
 340
 341                         gd->bd->bi_dram[current_bank - 1].start =
 342                                 gd->bd->bi_dram[current_bank].start;
 343                         gd->bd->bi_dram[current_bank - 1].size =
 344                                 gd->bd->bi_dram[current_bank].size;
 345
 346                         gd->bd->bi_dram[current_bank].start = start;
 347                         gd->bd->bi_dram[current_bank].size = size;
 348                 }
 349                 current_bank--;
 350         }
 351 }
 352
 353 int dram_init_banksize(void)
 354 {
 355         sc_rm_mr_t mr;
 356         sc_faddr_t start, end, end1, end2;
 357         int i = 0;
 358         int err;
 359
 360         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 361         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 362
 363         for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
 364                 err = get_owned_memreg(mr, &start, &end);
 365                 if (!err) {
 366                         start = roundup(start, MEMSTART_ALIGNMENT);
 367                         if (start > end) /* Small memory region, no use it */
 368                                 continue;
 369
 370                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 371                                 gd->bd->bi_dram[i].start = start;
 372
 373                                 if ((end + 1) <= end1)
 374                                         gd->bd->bi_dram[i].size =
 375                                                 end - start + 1;
 376                                 else
 377                                         gd->bd->bi_dram[i].size = end1 - start;
 378
 379                                 dram_bank_sort(i);
 380                                 i++;
 381                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 382                                 gd->bd->bi_dram[i].start = start;
 383
 384                                 if ((end + 1) <= end2)
 385                                         gd->bd->bi_dram[i].size =
 386                                                 end - start + 1;
 387                                 else
 388                                         gd->bd->bi_dram[i].size = end2 - start;
 389
 390                                 dram_bank_sort(i);
 391                                 i++;
 392                         }
 393                 }
 394         }
 395
 396         /* If error, set to the default value */
 397         if (!i) {
 398                 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 399                 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 400                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 401                 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static u64 get_block_attrs(sc_faddr_t addr_start)
 408 {
 409         u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
 410                 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 411
 412         if ((addr_start >= PHYS_SDRAM_1 &&
 413              addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
 414             (addr_start >= PHYS_SDRAM_2 &&
 415              addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
 416                 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
 417
 418         return attr;
 419 }
 420
 421 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
 422 {
 423         sc_faddr_t end1, end2;
 424
 425         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 426         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 427
 428         if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
 429                 if ((addr_end + 1) > end1)
 430                         return end1 - addr_start;
 431         } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
 432                 if ((addr_end + 1) > end2)
 433                         return end2 - addr_start;
 434         }
 435
 436         return (addr_end - addr_start + 1);
 437 }
 438
 439 #define MAX_PTE_ENTRIES 512
 440 #define MAX_MEM_MAP_REGIONS 16
 441
 442 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
 443 struct mm_region *mem_map = imx8_mem_map;
 444
 445 void enable_caches(void)
 446 {
 447         sc_rm_mr_t mr;
 448         sc_faddr_t start, end;
 449         int err, i;
 450
 451         /* Create map for registers access from 0x1c000000 to 0x80000000*/
 452         imx8_mem_map[0].virt = 0x1c000000UL;
 453         imx8_mem_map[0].phys = 0x1c000000UL;
 454         imx8_mem_map[0].size = 0x64000000UL;
 455         imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 456                          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 457
 458         i = 1;
 459         for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
 460                 err = get_owned_memreg(mr, &start, &end);
 461                 if (!err) {
 462                         imx8_mem_map[i].virt = start;
 463                         imx8_mem_map[i].phys = start;
 464                         imx8_mem_map[i].size = get_block_size(start, end);
 465                         imx8_mem_map[i].attrs = get_block_attrs(start);
 466                         i++;
 467                 }
 468         }
 469
 470         if (i < MAX_MEM_MAP_REGIONS) {
 471                 imx8_mem_map[i].size = 0;
 472                 imx8_mem_map[i].attrs = 0;
 473         } else {
 474                 puts("Error, need more MEM MAP REGIONS reserved\n");
 475                 icache_enable();
 476                 return;
 477         }
 478
 479         for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
 480                 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
 481                       i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
 482                       imx8_mem_map[i].size, imx8_mem_map[i].attrs);
 483         }
 484
 485         icache_enable();
 486         dcache_enable();
 487 }
 488
 489 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 490 u64 get_page_table_size(void)
 491 {
 492         u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
 493         u64 size = 0;
 494
 495         /*
 496          * For each memory region, the max table size:
 497          * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
 498          */
 499         size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
 500
 501         /*
 502          * We need to duplicate our page table once to have an emergency pt to
 503          * resort to when splitting page tables later on
 504          */
 505         size *= 2;
 506
 507         /*
 508          * We may need to split page tables later on if dcache settings change,
 509          * so reserve up to 4 (random pick) page tables for that.
 510          */
 511         size += one_pt * 4;
 512
 513         return size;
 514 }
 515 #endif
 516
 517 #if defined(CONFIG_IMX8QM)
 518 #define FUSE_MAC0_WORD0 452
 519 #define FUSE_MAC0_WORD1 453
 520 #define FUSE_MAC1_WORD0 454
 521 #define FUSE_MAC1_WORD1 455
 522 #elif defined(CONFIG_IMX8QXP)
 523 #define FUSE_MAC0_WORD0 708
 524 #define FUSE_MAC0_WORD1 709
 525 #define FUSE_MAC1_WORD0 710
 526 #define FUSE_MAC1_WORD1 711
 527 #endif
 528
 529 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 530 {
 531         u32 word[2], val[2] = {};
 532         int i, ret;
 533
 534         if (dev_id == 0) {
 535                 word[0] = FUSE_MAC0_WORD0;
 536                 word[1] = FUSE_MAC0_WORD1;
 537         } else {
 538                 word[0] = FUSE_MAC1_WORD0;
 539                 word[1] = FUSE_MAC1_WORD1;
 540         }
 541
 542         for (i = 0; i < 2; i++) {
 543                 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
 544                 if (ret < 0)
 545                         goto err;
 546         }
 547
 548         mac[0] = val[0];
 549         mac[1] = val[0] >> 8;
 550         mac[2] = val[0] >> 16;
 551         mac[3] = val[0] >> 24;
 552         mac[4] = val[1];
 553         mac[5] = val[1] >> 8;
 554
 555         debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
 556               __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 557         return;
 558 err:
 559         printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
 560 }
 561
 562 u32 get_cpu_rev(void)
 563 {
 564         u32 id = 0, rev = 0;
 565         int ret;
 566
 567         ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
 568         if (ret)
 569                 return 0;
 570
 571         rev = (id >> 5)  & 0xf;
 572         id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */
 573
 574         return (id << 12) | rev;
 575 }