arch/arm/mach-imx/imx8/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <cpu.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <init.h>
  12 #include <dm/device-internal.h>
  13 #include <dm/lists.h>
  14 #include <dm/uclass.h>
  15 #include <errno.h>
  16 #include <spl.h>
  17 #include <thermal.h>
  18 #include <asm/arch/sci/sci.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch-imx/cpu.h>
  21 #include <asm/armv8/cpu.h>
  22 #include <asm/armv8/mmu.h>
  23 #include <asm/setup.h>
  24 #include <asm/mach-imx/boot_mode.h>
  25 #include <spl.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define BT_PASSOVER_TAG 0x504F
  30 struct pass_over_info_t *get_pass_over_info(void)
  31 {
  32         struct pass_over_info_t *p =
  33                 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
  34
  35         if (p->barker != BT_PASSOVER_TAG ||
  36             p->len != sizeof(struct pass_over_info_t))
  37                 return NULL;
  38
  39         return p;
  40 }
  41
  42 int arch_cpu_init(void)
  43 {
  44 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
  45         spl_save_restore_data();
  46 #endif
  47
  48 #ifdef CONFIG_SPL_BUILD
  49         struct pass_over_info_t *pass_over;
  50
  51         if (is_soc_rev(CHIP_REV_A)) {
  52                 pass_over = get_pass_over_info();
  53                 if (pass_over && pass_over->g_ap_mu == 0) {
  54                         /*
  55                          * When ap_mu is 0, means the U-Boot booted
  56                          * from first container
  57                          */
  58                         sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
  59                 }
  60         }
  61 #endif
  62
  63         return 0;
  64 }
  65
  66 int arch_cpu_init_dm(void)
  67 {
  68         struct udevice *devp;
  69         int node, ret;
  70
  71         node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
  72
  73         ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
  74         if (ret) {
  75                 printf("could not get scu %d\n", ret);
  76                 return ret;
  77         }
  78
  79         if (is_imx8qm()) {
  80                 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
  81                                                     SC_PM_PW_MODE_ON);
  82                 if (ret)
  83                         return ret;
  84         }
  85
  86         return 0;
  87 }
  88
  89 int print_bootinfo(void)
  90 {
  91         enum boot_device bt_dev = get_boot_device();
  92
  93         puts("Boot:  ");
  94         switch (bt_dev) {
  95         case SD1_BOOT:
  96                 puts("SD0\n");
  97                 break;
  98         case SD2_BOOT:
  99                 puts("SD1\n");
 100                 break;
 101         case SD3_BOOT:
 102                 puts("SD2\n");
 103                 break;
 104         case MMC1_BOOT:
 105                 puts("MMC0\n");
 106                 break;
 107         case MMC2_BOOT:
 108                 puts("MMC1\n");
 109                 break;
 110         case MMC3_BOOT:
 111                 puts("MMC2\n");
 112                 break;
 113         case FLEXSPI_BOOT:
 114                 puts("FLEXSPI\n");
 115                 break;
 116         case SATA_BOOT:
 117                 puts("SATA\n");
 118                 break;
 119         case NAND_BOOT:
 120                 puts("NAND\n");
 121                 break;
 122         case USB_BOOT:
 123                 puts("USB\n");
 124                 break;
 125         default:
 126                 printf("Unknown device %u\n", bt_dev);
 127                 break;
 128         }
 129
 130         return 0;
 131 }
 132
 133 enum boot_device get_boot_device(void)
 134 {
 135         enum boot_device boot_dev = SD1_BOOT;
 136
 137         sc_rsrc_t dev_rsrc;
 138
 139         sc_misc_get_boot_dev(-1, &dev_rsrc);
 140
 141         switch (dev_rsrc) {
 142         case SC_R_SDHC_0:
 143                 boot_dev = MMC1_BOOT;
 144                 break;
 145         case SC_R_SDHC_1:
 146                 boot_dev = SD2_BOOT;
 147                 break;
 148         case SC_R_SDHC_2:
 149                 boot_dev = SD3_BOOT;
 150                 break;
 151         case SC_R_NAND:
 152                 boot_dev = NAND_BOOT;
 153                 break;
 154         case SC_R_FSPI_0:
 155                 boot_dev = FLEXSPI_BOOT;
 156                 break;
 157         case SC_R_SATA_0:
 158                 boot_dev = SATA_BOOT;
 159                 break;
 160         case SC_R_USB_0:
 161         case SC_R_USB_1:
 162         case SC_R_USB_2:
 163                 boot_dev = USB_BOOT;
 164                 break;
 165         default:
 166                 break;
 167         }
 168
 169         return boot_dev;
 170 }
 171
 172 #ifdef CONFIG_SERIAL_TAG
 173 #define FUSE_UNIQUE_ID_WORD0 16
 174 #define FUSE_UNIQUE_ID_WORD1 17
 175 void get_board_serial(struct tag_serialnr *serialnr)
 176 {
 177         sc_err_t err;
 178         u32 val1 = 0, val2 = 0;
 179         u32 word1, word2;
 180
 181         if (!serialnr)
 182                 return;
 183
 184         word1 = FUSE_UNIQUE_ID_WORD0;
 185         word2 = FUSE_UNIQUE_ID_WORD1;
 186
 187         err = sc_misc_otp_fuse_read(-1, word1, &val1);
 188         if (err != SC_ERR_NONE) {
 189                 printf("%s fuse %d read error: %d\n", __func__, word1, err);
 190                 return;
 191         }
 192
 193         err = sc_misc_otp_fuse_read(-1, word2, &val2);
 194         if (err != SC_ERR_NONE) {
 195                 printf("%s fuse %d read error: %d\n", __func__, word2, err);
 196                 return;
 197         }
 198         serialnr->low = val1;
 199         serialnr->high = val2;
 200 }
 201 #endif /*CONFIG_SERIAL_TAG*/
 202
 203 #ifdef CONFIG_ENV_IS_IN_MMC
 204 __weak int board_mmc_get_env_dev(int devno)
 205 {
 206         return CONFIG_SYS_MMC_ENV_DEV;
 207 }
 208
 209 int mmc_get_env_dev(void)
 210 {
 211         sc_rsrc_t dev_rsrc;
 212         int devno;
 213
 214         sc_misc_get_boot_dev(-1, &dev_rsrc);
 215
 216         switch (dev_rsrc) {
 217         case SC_R_SDHC_0:
 218                 devno = 0;
 219                 break;
 220         case SC_R_SDHC_1:
 221                 devno = 1;
 222                 break;
 223         case SC_R_SDHC_2:
 224                 devno = 2;
 225                 break;
 226         default:
 227                 /* If not boot from sd/mmc, use default value */
 228                 return CONFIG_SYS_MMC_ENV_DEV;
 229         }
 230
 231         return board_mmc_get_env_dev(devno);
 232 }
 233 #endif
 234
 235 #define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */
 236
 237 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
 238                             sc_faddr_t *addr_end)
 239 {
 240         sc_faddr_t start, end;
 241         int ret;
 242         bool owned;
 243
 244         owned = sc_rm_is_memreg_owned(-1, mr);
 245         if (owned) {
 246                 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
 247                 if (ret) {
 248                         printf("Memreg get info failed, %d\n", ret);
 249                         return -EINVAL;
 250                 }
 251                 debug("0x%llx -- 0x%llx\n", start, end);
 252                 *addr_start = start;
 253                 *addr_end = end;
 254
 255                 return 0;
 256         }
 257
 258         return -EINVAL;
 259 }
 260
 261 phys_size_t get_effective_memsize(void)
 262 {
 263         sc_rm_mr_t mr;
 264         sc_faddr_t start, end, end1, start_aligned;
 265         int err;
 266
 267         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 268
 269         for (mr = 0; mr < 64; mr++) {
 270                 err = get_owned_memreg(mr, &start, &end);
 271                 if (!err) {
 272                         start_aligned = roundup(start, MEMSTART_ALIGNMENT);
 273                         /* Too small memory region, not use it */
 274                         if (start_aligned > end)
 275                                 continue;
 276
 277                         /* Find the memory region runs the U-Boot */
 278                         if (start >= PHYS_SDRAM_1 && start <= end1 &&
 279                             (start <= CONFIG_SYS_TEXT_BASE &&
 280                             end >= CONFIG_SYS_TEXT_BASE)) {
 281                                 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
 282                                     PHYS_SDRAM_1_SIZE))
 283                                         return (end - PHYS_SDRAM_1 + 1);
 284                                 else
 285                                         return PHYS_SDRAM_1_SIZE;
 286                         }
 287                 }
 288         }
 289
 290         return PHYS_SDRAM_1_SIZE;
 291 }
 292
 293 int dram_init(void)
 294 {
 295         sc_rm_mr_t mr;
 296         sc_faddr_t start, end, end1, end2;
 297         int err;
 298
 299         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 300         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 301         for (mr = 0; mr < 64; mr++) {
 302                 err = get_owned_memreg(mr, &start, &end);
 303                 if (!err) {
 304                         start = roundup(start, MEMSTART_ALIGNMENT);
 305                         /* Too small memory region, not use it */
 306                         if (start > end)
 307                                 continue;
 308
 309                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 310                                 if ((end + 1) <= end1)
 311                                         gd->ram_size += end - start + 1;
 312                                 else
 313                                         gd->ram_size += end1 - start;
 314                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 315                                 if ((end + 1) <= end2)
 316                                         gd->ram_size += end - start + 1;
 317                                 else
 318                                         gd->ram_size += end2 - start;
 319                         }
 320                 }
 321         }
 322
 323         /* If error, set to the default value */
 324         if (!gd->ram_size) {
 325                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 326                 gd->ram_size += PHYS_SDRAM_2_SIZE;
 327         }
 328         return 0;
 329 }
 330
 331 static void dram_bank_sort(int current_bank)
 332 {
 333         phys_addr_t start;
 334         phys_size_t size;
 335
 336         while (current_bank > 0) {
 337                 if (gd->bd->bi_dram[current_bank - 1].start >
 338                     gd->bd->bi_dram[current_bank].start) {
 339                         start = gd->bd->bi_dram[current_bank - 1].start;
 340                         size = gd->bd->bi_dram[current_bank - 1].size;
 341
 342                         gd->bd->bi_dram[current_bank - 1].start =
 343                                 gd->bd->bi_dram[current_bank].start;
 344                         gd->bd->bi_dram[current_bank - 1].size =
 345                                 gd->bd->bi_dram[current_bank].size;
 346
 347                         gd->bd->bi_dram[current_bank].start = start;
 348                         gd->bd->bi_dram[current_bank].size = size;
 349                 }
 350                 current_bank--;
 351         }
 352 }
 353
 354 int dram_init_banksize(void)
 355 {
 356         sc_rm_mr_t mr;
 357         sc_faddr_t start, end, end1, end2;
 358         int i = 0;
 359         int err;
 360
 361         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 362         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 363
 364         for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
 365                 err = get_owned_memreg(mr, &start, &end);
 366                 if (!err) {
 367                         start = roundup(start, MEMSTART_ALIGNMENT);
 368                         if (start > end) /* Small memory region, no use it */
 369                                 continue;
 370
 371                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 372                                 gd->bd->bi_dram[i].start = start;
 373
 374                                 if ((end + 1) <= end1)
 375                                         gd->bd->bi_dram[i].size =
 376                                                 end - start + 1;
 377                                 else
 378                                         gd->bd->bi_dram[i].size = end1 - start;
 379
 380                                 dram_bank_sort(i);
 381                                 i++;
 382                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 383                                 gd->bd->bi_dram[i].start = start;
 384
 385                                 if ((end + 1) <= end2)
 386                                         gd->bd->bi_dram[i].size =
 387                                                 end - start + 1;
 388                                 else
 389                                         gd->bd->bi_dram[i].size = end2 - start;
 390
 391                                 dram_bank_sort(i);
 392                                 i++;
 393                         }
 394                 }
 395         }
 396
 397         /* If error, set to the default value */
 398         if (!i) {
 399                 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 400                 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 401                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 402                 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 403         }
 404
 405         return 0;
 406 }
 407
 408 static u64 get_block_attrs(sc_faddr_t addr_start)
 409 {
 410         u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
 411                 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 412
 413         if ((addr_start >= PHYS_SDRAM_1 &&
 414              addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
 415             (addr_start >= PHYS_SDRAM_2 &&
 416              addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
 417                 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
 418
 419         return attr;
 420 }
 421
 422 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
 423 {
 424         sc_faddr_t end1, end2;
 425
 426         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 427         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 428
 429         if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
 430                 if ((addr_end + 1) > end1)
 431                         return end1 - addr_start;
 432         } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
 433                 if ((addr_end + 1) > end2)
 434                         return end2 - addr_start;
 435         }
 436
 437         return (addr_end - addr_start + 1);
 438 }
 439
 440 #define MAX_PTE_ENTRIES 512
 441 #define MAX_MEM_MAP_REGIONS 16
 442
 443 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
 444 struct mm_region *mem_map = imx8_mem_map;
 445
 446 void enable_caches(void)
 447 {
 448         sc_rm_mr_t mr;
 449         sc_faddr_t start, end;
 450         int err, i;
 451
 452         /* Create map for registers access from 0x1c000000 to 0x80000000*/
 453         imx8_mem_map[0].virt = 0x1c000000UL;
 454         imx8_mem_map[0].phys = 0x1c000000UL;
 455         imx8_mem_map[0].size = 0x64000000UL;
 456         imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 457                          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 458
 459         i = 1;
 460         for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
 461                 err = get_owned_memreg(mr, &start, &end);
 462                 if (!err) {
 463                         imx8_mem_map[i].virt = start;
 464                         imx8_mem_map[i].phys = start;
 465                         imx8_mem_map[i].size = get_block_size(start, end);
 466                         imx8_mem_map[i].attrs = get_block_attrs(start);
 467                         i++;
 468                 }
 469         }
 470
 471         if (i < MAX_MEM_MAP_REGIONS) {
 472                 imx8_mem_map[i].size = 0;
 473                 imx8_mem_map[i].attrs = 0;
 474         } else {
 475                 puts("Error, need more MEM MAP REGIONS reserved\n");
 476                 icache_enable();
 477                 return;
 478         }
 479
 480         for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
 481                 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
 482                       i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
 483                       imx8_mem_map[i].size, imx8_mem_map[i].attrs);
 484         }
 485
 486         icache_enable();
 487         dcache_enable();
 488 }
 489
 490 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 491 u64 get_page_table_size(void)
 492 {
 493         u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
 494         u64 size = 0;
 495
 496         /*
 497          * For each memory region, the max table size:
 498          * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
 499          */
 500         size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
 501
 502         /*
 503          * We need to duplicate our page table once to have an emergency pt to
 504          * resort to when splitting page tables later on
 505          */
 506         size *= 2;
 507
 508         /*
 509          * We may need to split page tables later on if dcache settings change,
 510          * so reserve up to 4 (random pick) page tables for that.
 511          */
 512         size += one_pt * 4;
 513
 514         return size;
 515 }
 516 #endif
 517
 518 #if defined(CONFIG_IMX8QM)
 519 #define FUSE_MAC0_WORD0 452
 520 #define FUSE_MAC0_WORD1 453
 521 #define FUSE_MAC1_WORD0 454
 522 #define FUSE_MAC1_WORD1 455
 523 #elif defined(CONFIG_IMX8QXP)
 524 #define FUSE_MAC0_WORD0 708
 525 #define FUSE_MAC0_WORD1 709
 526 #define FUSE_MAC1_WORD0 710
 527 #define FUSE_MAC1_WORD1 711
 528 #endif
 529
 530 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 531 {
 532         u32 word[2], val[2] = {};
 533         int i, ret;
 534
 535         if (dev_id == 0) {
 536                 word[0] = FUSE_MAC0_WORD0;
 537                 word[1] = FUSE_MAC0_WORD1;
 538         } else {
 539                 word[0] = FUSE_MAC1_WORD0;
 540                 word[1] = FUSE_MAC1_WORD1;
 541         }
 542
 543         for (i = 0; i < 2; i++) {
 544                 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
 545                 if (ret < 0)
 546                         goto err;
 547         }
 548
 549         mac[0] = val[0];
 550         mac[1] = val[0] >> 8;
 551         mac[2] = val[0] >> 16;
 552         mac[3] = val[0] >> 24;
 553         mac[4] = val[1];
 554         mac[5] = val[1] >> 8;
 555
 556         debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
 557               __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 558         return;
 559 err:
 560         printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
 561 }
 562
 563 u32 get_cpu_rev(void)
 564 {
 565         u32 id = 0, rev = 0;
 566         int ret;
 567
 568         ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
 569         if (ret)
 570                 return 0;
 571
 572         rev = (id >> 5)  & 0xf;
 573         id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */
 574
 575         return (id << 12) | rev;
 576 }
 577
 578 void board_boot_order(u32 *spl_boot_list)
 579 {
 580         spl_boot_list[0] = spl_boot_device();
 581
 582         if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
 583                 /* Check whether we own the flexspi0, if not, use NOR boot */
 584                 if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
 585                         spl_boot_list[0] = BOOT_DEVICE_NOR;
 586         }
 587 }