arch/arm/mach-imx/imx8/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <cpu.h>
   9 #include <dm.h>
  10 #include <dm/device-internal.h>
  11 #include <dm/lists.h>
  12 #include <dm/uclass.h>
  13 #include <errno.h>
  14 #include <thermal.h>
  15 #include <asm/arch/sci/sci.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch-imx/cpu.h>
  18 #include <asm/armv8/cpu.h>
  19 #include <asm/armv8/mmu.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define BT_PASSOVER_TAG 0x504F
  25 struct pass_over_info_t *get_pass_over_info(void)
  26 {
  27         struct pass_over_info_t *p =
  28                 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
  29
  30         if (p->barker != BT_PASSOVER_TAG ||
  31             p->len != sizeof(struct pass_over_info_t))
  32                 return NULL;
  33
  34         return p;
  35 }
  36
  37 int arch_cpu_init(void)
  38 {
  39 #ifdef CONFIG_SPL_BUILD
  40         struct pass_over_info_t *pass_over;
  41
  42         if (is_soc_rev(CHIP_REV_A)) {
  43                 pass_over = get_pass_over_info();
  44                 if (pass_over && pass_over->g_ap_mu == 0) {
  45                         /*
  46                          * When ap_mu is 0, means the U-Boot booted
  47                          * from first container
  48                          */
  49                         sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
  50                 }
  51         }
  52 #endif
  53
  54         return 0;
  55 }
  56
  57 int arch_cpu_init_dm(void)
  58 {
  59         struct udevice *devp;
  60         int node, ret;
  61
  62         node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
  63         ret = device_bind_driver_to_node(gd->dm_root, "imx8_scu", "imx8_scu",
  64                                          offset_to_ofnode(node), &devp);
  65
  66         if (ret) {
  67                 printf("could not find scu %d\n", ret);
  68                 return ret;
  69         }
  70
  71         ret = device_probe(devp);
  72         if (ret) {
  73                 printf("scu probe failed %d\n", ret);
  74                 return ret;
  75         }
  76
  77         return 0;
  78 }
  79
  80 int print_bootinfo(void)
  81 {
  82         enum boot_device bt_dev = get_boot_device();
  83
  84         puts("Boot:  ");
  85         switch (bt_dev) {
  86         case SD1_BOOT:
  87                 puts("SD0\n");
  88                 break;
  89         case SD2_BOOT:
  90                 puts("SD1\n");
  91                 break;
  92         case SD3_BOOT:
  93                 puts("SD2\n");
  94                 break;
  95         case MMC1_BOOT:
  96                 puts("MMC0\n");
  97                 break;
  98         case MMC2_BOOT:
  99                 puts("MMC1\n");
 100                 break;
 101         case MMC3_BOOT:
 102                 puts("MMC2\n");
 103                 break;
 104         case FLEXSPI_BOOT:
 105                 puts("FLEXSPI\n");
 106                 break;
 107         case SATA_BOOT:
 108                 puts("SATA\n");
 109                 break;
 110         case NAND_BOOT:
 111                 puts("NAND\n");
 112                 break;
 113         case USB_BOOT:
 114                 puts("USB\n");
 115                 break;
 116         default:
 117                 printf("Unknown device %u\n", bt_dev);
 118                 break;
 119         }
 120
 121         return 0;
 122 }
 123
 124 enum boot_device get_boot_device(void)
 125 {
 126         enum boot_device boot_dev = SD1_BOOT;
 127
 128         sc_rsrc_t dev_rsrc;
 129
 130         sc_misc_get_boot_dev(-1, &dev_rsrc);
 131
 132         switch (dev_rsrc) {
 133         case SC_R_SDHC_0:
 134                 boot_dev = MMC1_BOOT;
 135                 break;
 136         case SC_R_SDHC_1:
 137                 boot_dev = SD2_BOOT;
 138                 break;
 139         case SC_R_SDHC_2:
 140                 boot_dev = SD3_BOOT;
 141                 break;
 142         case SC_R_NAND:
 143                 boot_dev = NAND_BOOT;
 144                 break;
 145         case SC_R_FSPI_0:
 146                 boot_dev = FLEXSPI_BOOT;
 147                 break;
 148         case SC_R_SATA_0:
 149                 boot_dev = SATA_BOOT;
 150                 break;
 151         case SC_R_USB_0:
 152         case SC_R_USB_1:
 153         case SC_R_USB_2:
 154                 boot_dev = USB_BOOT;
 155                 break;
 156         default:
 157                 break;
 158         }
 159
 160         return boot_dev;
 161 }
 162
 163 #ifdef CONFIG_ENV_IS_IN_MMC
 164 __weak int board_mmc_get_env_dev(int devno)
 165 {
 166         return CONFIG_SYS_MMC_ENV_DEV;
 167 }
 168
 169 int mmc_get_env_dev(void)
 170 {
 171         sc_rsrc_t dev_rsrc;
 172         int devno;
 173
 174         sc_misc_get_boot_dev(-1, &dev_rsrc);
 175
 176         switch (dev_rsrc) {
 177         case SC_R_SDHC_0:
 178                 devno = 0;
 179                 break;
 180         case SC_R_SDHC_1:
 181                 devno = 1;
 182                 break;
 183         case SC_R_SDHC_2:
 184                 devno = 2;
 185                 break;
 186         default:
 187                 /* If not boot from sd/mmc, use default value */
 188                 return CONFIG_SYS_MMC_ENV_DEV;
 189         }
 190
 191         return board_mmc_get_env_dev(devno);
 192 }
 193 #endif
 194
 195 #define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */
 196
 197 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
 198                             sc_faddr_t *addr_end)
 199 {
 200         sc_faddr_t start, end;
 201         int ret;
 202         bool owned;
 203
 204         owned = sc_rm_is_memreg_owned(-1, mr);
 205         if (owned) {
 206                 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
 207                 if (ret) {
 208                         printf("Memreg get info failed, %d\n", ret);
 209                         return -EINVAL;
 210                 }
 211                 debug("0x%llx -- 0x%llx\n", start, end);
 212                 *addr_start = start;
 213                 *addr_end = end;
 214
 215                 return 0;
 216         }
 217
 218         return -EINVAL;
 219 }
 220
 221 phys_size_t get_effective_memsize(void)
 222 {
 223         sc_rm_mr_t mr;
 224         sc_faddr_t start, end, end1;
 225         int err;
 226
 227         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 228
 229         for (mr = 0; mr < 64; mr++) {
 230                 err = get_owned_memreg(mr, &start, &end);
 231                 if (!err) {
 232                         start = roundup(start, MEMSTART_ALIGNMENT);
 233                         /* Too small memory region, not use it */
 234                         if (start > end)
 235                                 continue;
 236
 237                         /* Find the memory region runs the U-Boot */
 238                         if (start >= PHYS_SDRAM_1 && start <= end1 &&
 239                             (start <= CONFIG_SYS_TEXT_BASE &&
 240                             end >= CONFIG_SYS_TEXT_BASE)) {
 241                                 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
 242                                     PHYS_SDRAM_1_SIZE))
 243                                         return (end - PHYS_SDRAM_1 + 1);
 244                                 else
 245                                         return PHYS_SDRAM_1_SIZE;
 246                         }
 247                 }
 248         }
 249
 250         return PHYS_SDRAM_1_SIZE;
 251 }
 252
 253 int dram_init(void)
 254 {
 255         sc_rm_mr_t mr;
 256         sc_faddr_t start, end, end1, end2;
 257         int err;
 258
 259         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 260         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 261         for (mr = 0; mr < 64; mr++) {
 262                 err = get_owned_memreg(mr, &start, &end);
 263                 if (!err) {
 264                         start = roundup(start, MEMSTART_ALIGNMENT);
 265                         /* Too small memory region, not use it */
 266                         if (start > end)
 267                                 continue;
 268
 269                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 270                                 if ((end + 1) <= end1)
 271                                         gd->ram_size += end - start + 1;
 272                                 else
 273                                         gd->ram_size += end1 - start;
 274                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 275                                 if ((end + 1) <= end2)
 276                                         gd->ram_size += end - start + 1;
 277                                 else
 278                                         gd->ram_size += end2 - start;
 279                         }
 280                 }
 281         }
 282
 283         /* If error, set to the default value */
 284         if (!gd->ram_size) {
 285                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 286                 gd->ram_size += PHYS_SDRAM_2_SIZE;
 287         }
 288         return 0;
 289 }
 290
 291 static void dram_bank_sort(int current_bank)
 292 {
 293         phys_addr_t start;
 294         phys_size_t size;
 295
 296         while (current_bank > 0) {
 297                 if (gd->bd->bi_dram[current_bank - 1].start >
 298                     gd->bd->bi_dram[current_bank].start) {
 299                         start = gd->bd->bi_dram[current_bank - 1].start;
 300                         size = gd->bd->bi_dram[current_bank - 1].size;
 301
 302                         gd->bd->bi_dram[current_bank - 1].start =
 303                                 gd->bd->bi_dram[current_bank].start;
 304                         gd->bd->bi_dram[current_bank - 1].size =
 305                                 gd->bd->bi_dram[current_bank].size;
 306
 307                         gd->bd->bi_dram[current_bank].start = start;
 308                         gd->bd->bi_dram[current_bank].size = size;
 309                 }
 310                 current_bank--;
 311         }
 312 }
 313
 314 int dram_init_banksize(void)
 315 {
 316         sc_rm_mr_t mr;
 317         sc_faddr_t start, end, end1, end2;
 318         int i = 0;
 319         int err;
 320
 321         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 322         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 323
 324         for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
 325                 err = get_owned_memreg(mr, &start, &end);
 326                 if (!err) {
 327                         start = roundup(start, MEMSTART_ALIGNMENT);
 328                         if (start > end) /* Small memory region, no use it */
 329                                 continue;
 330
 331                         if (start >= PHYS_SDRAM_1 && start <= end1) {
 332                                 gd->bd->bi_dram[i].start = start;
 333
 334                                 if ((end + 1) <= end1)
 335                                         gd->bd->bi_dram[i].size =
 336                                                 end - start + 1;
 337                                 else
 338                                         gd->bd->bi_dram[i].size = end1 - start;
 339
 340                                 dram_bank_sort(i);
 341                                 i++;
 342                         } else if (start >= PHYS_SDRAM_2 && start <= end2) {
 343                                 gd->bd->bi_dram[i].start = start;
 344
 345                                 if ((end + 1) <= end2)
 346                                         gd->bd->bi_dram[i].size =
 347                                                 end - start + 1;
 348                                 else
 349                                         gd->bd->bi_dram[i].size = end2 - start;
 350
 351                                 dram_bank_sort(i);
 352                                 i++;
 353                         }
 354                 }
 355         }
 356
 357         /* If error, set to the default value */
 358         if (!i) {
 359                 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 360                 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 361                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 362                 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 363         }
 364
 365         return 0;
 366 }
 367
 368 static u64 get_block_attrs(sc_faddr_t addr_start)
 369 {
 370         u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
 371                 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 372
 373         if ((addr_start >= PHYS_SDRAM_1 &&
 374              addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
 375             (addr_start >= PHYS_SDRAM_2 &&
 376              addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
 377                 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
 378
 379         return attr;
 380 }
 381
 382 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
 383 {
 384         sc_faddr_t end1, end2;
 385
 386         end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
 387         end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
 388
 389         if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
 390                 if ((addr_end + 1) > end1)
 391                         return end1 - addr_start;
 392         } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
 393                 if ((addr_end + 1) > end2)
 394                         return end2 - addr_start;
 395         }
 396
 397         return (addr_end - addr_start + 1);
 398 }
 399
 400 #define MAX_PTE_ENTRIES 512
 401 #define MAX_MEM_MAP_REGIONS 16
 402
 403 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
 404 struct mm_region *mem_map = imx8_mem_map;
 405
 406 void enable_caches(void)
 407 {
 408         sc_rm_mr_t mr;
 409         sc_faddr_t start, end;
 410         int err, i;
 411
 412         /* Create map for registers access from 0x1c000000 to 0x80000000*/
 413         imx8_mem_map[0].virt = 0x1c000000UL;
 414         imx8_mem_map[0].phys = 0x1c000000UL;
 415         imx8_mem_map[0].size = 0x64000000UL;
 416         imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 417                          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 418
 419         i = 1;
 420         for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
 421                 err = get_owned_memreg(mr, &start, &end);
 422                 if (!err) {
 423                         imx8_mem_map[i].virt = start;
 424                         imx8_mem_map[i].phys = start;
 425                         imx8_mem_map[i].size = get_block_size(start, end);
 426                         imx8_mem_map[i].attrs = get_block_attrs(start);
 427                         i++;
 428                 }
 429         }
 430
 431         if (i < MAX_MEM_MAP_REGIONS) {
 432                 imx8_mem_map[i].size = 0;
 433                 imx8_mem_map[i].attrs = 0;
 434         } else {
 435                 puts("Error, need more MEM MAP REGIONS reserved\n");
 436                 icache_enable();
 437                 return;
 438         }
 439
 440         for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
 441                 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
 442                       i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
 443                       imx8_mem_map[i].size, imx8_mem_map[i].attrs);
 444         }
 445
 446         icache_enable();
 447         dcache_enable();
 448 }
 449
 450 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 451 u64 get_page_table_size(void)
 452 {
 453         u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
 454         u64 size = 0;
 455
 456         /*
 457          * For each memory region, the max table size:
 458          * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
 459          */
 460         size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
 461
 462         /*
 463          * We need to duplicate our page table once to have an emergency pt to
 464          * resort to when splitting page tables later on
 465          */
 466         size *= 2;
 467
 468         /*
 469          * We may need to split page tables later on if dcache settings change,
 470          * so reserve up to 4 (random pick) page tables for that.
 471          */
 472         size += one_pt * 4;
 473
 474         return size;
 475 }
 476 #endif
 477
 478 #define FUSE_MAC0_WORD0 708
 479 #define FUSE_MAC0_WORD1 709
 480 #define FUSE_MAC1_WORD0 710
 481 #define FUSE_MAC1_WORD1 711
 482
 483 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 484 {
 485         u32 word[2], val[2] = {};
 486         int i, ret;
 487
 488         if (dev_id == 0) {
 489                 word[0] = FUSE_MAC0_WORD0;
 490                 word[1] = FUSE_MAC0_WORD1;
 491         } else {
 492                 word[0] = FUSE_MAC1_WORD0;
 493                 word[1] = FUSE_MAC1_WORD1;
 494         }
 495
 496         for (i = 0; i < 2; i++) {
 497                 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
 498                 if (ret < 0)
 499                         goto err;
 500         }
 501
 502         mac[0] = val[0];
 503         mac[1] = val[0] >> 8;
 504         mac[2] = val[0] >> 16;
 505         mac[3] = val[0] >> 24;
 506         mac[4] = val[1];
 507         mac[5] = val[1] >> 8;
 508
 509         debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
 510               __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 511         return;
 512 err:
 513         printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
 514 }
 515
 516 u32 get_cpu_rev(void)
 517 {
 518         u32 id = 0, rev = 0;
 519         int ret;
 520
 521         ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
 522         if (ret)
 523                 return 0;
 524
 525         rev = (id >> 5)  & 0xf;
 526         id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */
 527
 528         return (id << 12) | rev;
 529 }
 530
 531 #if CONFIG_IS_ENABLED(CPU)
 532 struct cpu_imx_platdata {
 533         const char *name;
 534         const char *rev;
 535         const char *type;
 536         u32 cpurev;
 537         u32 freq_mhz;
 538 };
 539
 540 const char *get_imx8_type(u32 imxtype)
 541 {
 542         switch (imxtype) {
 543         case MXC_CPU_IMX8QXP:
 544         case MXC_CPU_IMX8QXP_A0:
 545                 return "QXP";
 546         case MXC_CPU_IMX8QM:
 547                 return "QM";
 548         default:
 549                 return "??";
 550         }
 551 }
 552
 553 const char *get_imx8_rev(u32 rev)
 554 {
 555         switch (rev) {
 556         case CHIP_REV_A:
 557                 return "A";
 558         case CHIP_REV_B:
 559                 return "B";
 560         default:
 561                 return "?";
 562         }
 563 }
 564
 565 const char *get_core_name(void)
 566 {
 567         if (is_cortex_a35())
 568                 return "A35";
 569         else if (is_cortex_a53())
 570                 return "A53";
 571         else if (is_cortex_a72())
 572                 return "A72";
 573         else
 574                 return "?";
 575 }
 576
 577 #if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
 578 static int cpu_imx_get_temp(void)
 579 {
 580         struct udevice *thermal_dev;
 581         int cpu_tmp, ret;
 582
 583         ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
 584                                         &thermal_dev);
 585
 586         if (!ret) {
 587                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 588                 if (ret)
 589                         return 0xdeadbeef;
 590         } else {
 591                 return 0xdeadbeef;
 592         }
 593
 594         return cpu_tmp;
 595 }
 596 #else
 597 static int cpu_imx_get_temp(void)
 598 {
 599         return 0;
 600 }
 601 #endif
 602
 603 int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
 604 {
 605         struct cpu_imx_platdata *plat = dev_get_platdata(dev);
 606         int ret;
 607
 608         if (size < 100)
 609                 return -ENOSPC;
 610
 611         ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
 612                        plat->type, plat->rev, plat->name, plat->freq_mhz);
 613
 614         if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
 615                 buf = buf + ret;
 616                 size = size - ret;
 617                 ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
 618         }
 619
 620         snprintf(buf + ret, size - ret, "\n");
 621
 622         return 0;
 623 }
 624
 625 static int cpu_imx_get_info(struct udevice *dev, struct cpu_info *info)
 626 {
 627         struct cpu_imx_platdata *plat = dev_get_platdata(dev);
 628
 629         info->cpu_freq = plat->freq_mhz * 1000;
 630         info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
 631         return 0;
 632 }
 633
 634 static int cpu_imx_get_count(struct udevice *dev)
 635 {
 636         return 4;
 637 }
 638
 639 static int cpu_imx_get_vendor(struct udevice *dev,  char *buf, int size)
 640 {
 641         snprintf(buf, size, "NXP");
 642         return 0;
 643 }
 644
 645 static const struct cpu_ops cpu_imx8_ops = {
 646         .get_desc       = cpu_imx_get_desc,
 647         .get_info       = cpu_imx_get_info,
 648         .get_count      = cpu_imx_get_count,
 649         .get_vendor     = cpu_imx_get_vendor,
 650 };
 651
 652 static const struct udevice_id cpu_imx8_ids[] = {
 653         { .compatible = "arm,cortex-a35" },
 654         { .compatible = "arm,cortex-a53" },
 655         { }
 656 };
 657
 658 static ulong imx8_get_cpu_rate(void)
 659 {
 660         ulong rate;
 661         int ret;
 662         int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ?
 663                    SC_R_A53 : SC_R_A72;
 664
 665         ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
 666                                    (sc_pm_clock_rate_t *)&rate);
 667         if (ret) {
 668                 printf("Could not read CPU frequency: %d\n", ret);
 669                 return 0;
 670         }
 671
 672         return rate;
 673 }
 674
 675 static int imx8_cpu_probe(struct udevice *dev)
 676 {
 677         struct cpu_imx_platdata *plat = dev_get_platdata(dev);
 678         u32 cpurev;
 679
 680         cpurev = get_cpu_rev();
 681         plat->cpurev = cpurev;
 682         plat->name = get_core_name();
 683         plat->rev = get_imx8_rev(cpurev & 0xFFF);
 684         plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
 685         plat->freq_mhz = imx8_get_cpu_rate() / 1000000;
 686         return 0;
 687 }
 688
 689 U_BOOT_DRIVER(cpu_imx8_drv) = {
 690         .name           = "imx8x_cpu",
 691         .id             = UCLASS_CPU,
 692         .of_match       = cpu_imx8_ids,
 693         .ops            = &cpu_imx8_ops,
 694         .probe          = imx8_cpu_probe,
 695         .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata),
 696         .flags          = DM_FLAG_PRE_RELOC,
 697 };
 698 #endif