1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
13 #include <linux/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <imx_thermal.h>
21 #include <ipu_pixfmt.h>
25 #ifdef CONFIG_FSL_ESDHC_IMX
26 #include <fsl_esdhc_imx.h>
29 static u32 reset_cause = -1;
31 u32 get_imx_reset_cause(void)
33 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
35 if (reset_cause == -1) {
36 reset_cause = readl(&src_regs->srsr);
37 /* preserve the value for U-Boot proper */
38 #if !defined(CONFIG_SPL_BUILD)
39 writel(reset_cause, &src_regs->srsr);
46 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
47 static char *get_reset_cause(void)
49 switch (get_imx_reset_cause()) {
74 #elif defined(CONFIG_IMX8M)
86 return "unknown reset";
91 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
93 const char *get_imx_type(u32 imxtype)
97 return "8MP"; /* Quad-core version of the imx8mp */
99 return "8MNano Quad"; /* Quad-core version */
100 case MXC_CPU_IMX8MND:
101 return "8MNano Dual"; /* Dual-core version */
102 case MXC_CPU_IMX8MNS:
103 return "8MNano Solo"; /* Single-core version */
104 case MXC_CPU_IMX8MNL:
105 return "8MNano QuadLite"; /* Quad-core Lite version */
106 case MXC_CPU_IMX8MNDL:
107 return "8MNano DualLite"; /* Dual-core Lite version */
108 case MXC_CPU_IMX8MNSL:
109 return "8MNano SoloLite"; /* Single-core Lite version */
111 return "8MMQ"; /* Quad-core version of the imx8mm */
112 case MXC_CPU_IMX8MML:
113 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
114 case MXC_CPU_IMX8MMD:
115 return "8MMD"; /* Dual-core version of the imx8mm */
116 case MXC_CPU_IMX8MMDL:
117 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
118 case MXC_CPU_IMX8MMS:
119 return "8MMS"; /* Single-core version of the imx8mm */
120 case MXC_CPU_IMX8MMSL:
121 return "8MMSL"; /* Single-core Lite version of the imx8mm */
123 return "8MQ"; /* Quad-core version of the imx8mq */
124 case MXC_CPU_IMX8MQL:
125 return "8MQLite"; /* Quad-core Lite version of the imx8mq */
127 return "8MD"; /* Dual-core version of the imx8mq */
129 return "7S"; /* Single-core version of the mx7 */
131 return "7D"; /* Dual-core version of the mx7 */
133 return "6QP"; /* Quad-Plus version of the mx6 */
135 return "6DP"; /* Dual-Plus version of the mx6 */
137 return "6Q"; /* Quad-core version of the mx6 */
139 return "6D"; /* Dual-core version of the mx6 */
141 return "6DL"; /* Dual Lite version of the mx6 */
142 case MXC_CPU_MX6SOLO:
143 return "6SOLO"; /* Solo version of the mx6 */
145 return "6SL"; /* Solo-Lite version of the mx6 */
147 return "6SLL"; /* SLL version of the mx6 */
149 return "6SX"; /* SoloX version of the mx6 */
151 return "6UL"; /* Ultra-Lite version of the mx6 */
153 return "6ULL"; /* ULL version of the mx6 */
155 return "6ULZ"; /* ULZ version of the mx6 */
165 int print_cpuinfo(void)
168 __maybe_unused u32 max_freq;
170 cpurev = get_cpu_rev();
172 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
173 struct udevice *thermal_dev;
174 int cpu_tmp, minc, maxc, ret;
176 printf("CPU: Freescale i.MX%s rev%d.%d",
177 get_imx_type((cpurev & 0x1FF000) >> 12),
178 (cpurev & 0x000F0) >> 4,
179 (cpurev & 0x0000F) >> 0);
180 max_freq = get_cpu_speed_grade_hz();
181 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
182 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
184 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
185 mxc_get_clock(MXC_ARM_CLK) / 1000000);
188 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
189 get_imx_type((cpurev & 0x1FF000) >> 12),
190 (cpurev & 0x000F0) >> 4,
191 (cpurev & 0x0000F) >> 0,
192 mxc_get_clock(MXC_ARM_CLK) / 1000000);
195 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
197 switch (get_cpu_temp_grade(&minc, &maxc)) {
198 case TEMP_AUTOMOTIVE:
199 puts("Automotive temperature grade ");
201 case TEMP_INDUSTRIAL:
202 puts("Industrial temperature grade ");
204 case TEMP_EXTCOMMERCIAL:
205 puts("Extended Commercial temperature grade ");
208 puts("Commercial temperature grade ");
211 printf("(%dC to %dC)", minc, maxc);
212 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
214 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
217 printf(" at %dC\n", cpu_tmp);
219 debug(" - invalid sensor data\n");
221 debug(" - invalid sensor device\n");
225 printf("Reset cause: %s\n", get_reset_cause());
230 int cpu_eth_init(bd_t *bis)
234 #if defined(CONFIG_FEC_MXC)
235 rc = fecmxc_initialize(bis);
241 #ifdef CONFIG_FSL_ESDHC_IMX
243 * Initializes on-chip MMC controllers.
244 * to override, implement board_mmc_init()
246 int cpu_mmc_init(bd_t *bis)
248 return fsl_esdhc_mmc_init(bis);
252 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
253 u32 get_ahb_clk(void)
255 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
258 reg = __raw_readl(&imx_ccm->cbcdr);
259 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
260 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
262 return get_periph_clk() / (ahb_podf + 1);
266 void arch_preboot_os(void)
268 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
271 #if defined(CONFIG_SATA)
274 #if defined(CONFIG_MX6)
275 disable_sata_clock();
279 #if defined(CONFIG_VIDEO_IPUV3)
280 /* disable video before launching O/S */
283 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
289 void set_chipselect_size(int const cs_size)
292 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
293 reg = readl(&iomuxc_regs->gpr[1]);
297 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
300 case CS0_64M_CS1_64M:
301 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
304 case CS0_64M_CS1_32M_CS2_32M:
305 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
308 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
309 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
313 printf("Unknown chip select size: %d\n", cs_size);
317 writel(reg, &iomuxc_regs->gpr[1]);
321 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
323 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
324 * defines a 2-bit SPEED_GRADING
326 #define OCOTP_TESTER3_SPEED_SHIFT 8
328 OCOTP_TESTER3_SPEED_GRADE0,
329 OCOTP_TESTER3_SPEED_GRADE1,
330 OCOTP_TESTER3_SPEED_GRADE2,
331 OCOTP_TESTER3_SPEED_GRADE3,
332 OCOTP_TESTER3_SPEED_GRADE4,
335 u32 get_cpu_speed_grade_hz(void)
337 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
338 struct fuse_bank *bank = &ocotp->bank[1];
339 struct fuse_bank1_regs *fuse =
340 (struct fuse_bank1_regs *)bank->fuse_regs;
343 val = readl(&fuse->tester3);
344 val >>= OCOTP_TESTER3_SPEED_SHIFT;
346 if (is_imx8mn() || is_imx8mp()) {
348 return 2300000000 - val * 100000000;
357 case OCOTP_TESTER3_SPEED_GRADE0:
359 case OCOTP_TESTER3_SPEED_GRADE1:
360 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
361 case OCOTP_TESTER3_SPEED_GRADE2:
362 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
363 case OCOTP_TESTER3_SPEED_GRADE3:
364 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
365 case OCOTP_TESTER3_SPEED_GRADE4:
373 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
374 * defines a 2-bit SPEED_GRADING
376 #define OCOTP_TESTER3_TEMP_SHIFT 6
378 u32 get_cpu_temp_grade(int *minc, int *maxc)
380 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
381 struct fuse_bank *bank = &ocotp->bank[1];
382 struct fuse_bank1_regs *fuse =
383 (struct fuse_bank1_regs *)bank->fuse_regs;
386 val = readl(&fuse->tester3);
387 val >>= OCOTP_TESTER3_TEMP_SHIFT;
391 if (val == TEMP_AUTOMOTIVE) {
394 } else if (val == TEMP_INDUSTRIAL) {
397 } else if (val == TEMP_EXTCOMMERCIAL) {
409 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
410 enum boot_device get_boot_device(void)
412 struct bootrom_sw_info **p =
413 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
415 enum boot_device boot_dev = SD1_BOOT;
416 u8 boot_type = (*p)->boot_dev_type;
417 u8 boot_instance = (*p)->boot_dev_instance;
421 boot_dev = boot_instance + SD1_BOOT;
424 boot_dev = boot_instance + MMC1_BOOT;
427 boot_dev = NAND_BOOT;
430 boot_dev = QSPI_BOOT;
433 boot_dev = WEIM_NOR_BOOT;
435 case BOOT_TYPE_SPINOR:
436 boot_dev = SPI_NOR_BOOT;
451 #ifdef CONFIG_NXP_BOARD_REVISION
452 int nxp_board_rev(void)
455 * Get Board ID information from OCOTP_GP1[15:8]
460 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
461 struct fuse_bank *bank = &ocotp->bank[4];
462 struct fuse_bank4_regs *fuse =
463 (struct fuse_bank4_regs *)bank->fuse_regs;
465 return (readl(&fuse->gp1) >> 8 & 0x0F);
468 char nxp_board_rev_string(void)
470 const char *rev = "A";
472 return (*rev + nxp_board_rev() - 1);