arch/arm/mach-davinci/timer.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2003
   4  * Texas Instruments <www.ti.com>
   5  *
   6  * (C) Copyright 2002
   7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8  * Marius Groeger <mgroeger@sysgo.de>
   9  *
  10  * (C) Copyright 2002
  11  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  12  * Alex Zuepke <azu@sysgo.de>
  13  *
  14  * (C) Copyright 2002-2004
  15  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  16  *
  17  * (C) Copyright 2004
  18  * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
  19  *
  20  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  21  */
  22
  23 #include <common.h>
  24 #include <init.h>
  25 #include <time.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/timer_defs.h>
  28 #include <div64.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 static struct davinci_timer * const timer =
  33         (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
  34
  35 #define TIMER_LOAD_VAL  0xffffffff
  36
  37 #define TIM_CLK_DIV     16
  38
  39 int timer_init(void)
  40 {
  41         /* We are using timer34 in unchained 32-bit mode, full speed */
  42         writel(0x0, &timer->tcr);
  43         writel(0x0, &timer->tgcr);
  44         writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
  45         writel(0x0, &timer->tim34);
  46         writel(TIMER_LOAD_VAL, &timer->prd34);
  47         writel(2 << 22, &timer->tcr);
  48         gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
  49         gd->arch.timer_reset_value = 0;
  50
  51         return(0);
  52 }
  53
  54 /*
  55  * Get the current 64 bit timer tick count
  56  */
  57 unsigned long long get_ticks(void)
  58 {
  59         unsigned long now = readl(&timer->tim34);
  60
  61         /* increment tbu if tbl has rolled over */
  62         if (now < gd->arch.tbl)
  63                 gd->arch.tbu++;
  64         gd->arch.tbl = now;
  65
  66         return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
  67 }
  68
  69 ulong get_timer(ulong base)
  70 {
  71         unsigned long long timer_diff;
  72
  73         timer_diff = get_ticks() - gd->arch.timer_reset_value;
  74
  75         return lldiv(timer_diff,
  76                      (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
  77 }
  78
  79 void __udelay(unsigned long usec)
  80 {
  81         unsigned long long endtime;
  82
  83         endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
  84                         1000000UL);
  85         endtime += get_ticks();
  86
  87         while (get_ticks() < endtime)
  88                 ;
  89 }
  90
  91 /*
  92  * This function is derived from PowerPC code (timebase clock frequency).
  93  * On ARM it returns the number of timer ticks per second.
  94  */
  95 ulong get_tbclk(void)
  96 {
  97         return gd->arch.timer_rate_hz;
  98 }
  99
 100 #ifdef CONFIG_HW_WATCHDOG
 101 static struct davinci_timer * const wdttimer =
 102         (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
 103
 104 /*
 105  * See prufw2.pdf for using Timer as a WDT
 106  */
 107 void davinci_hw_watchdog_enable(void)
 108 {
 109         writel(0x0, &wdttimer->tcr);
 110         writel(0x0, &wdttimer->tgcr);
 111         /* TIMMODE = 2h */
 112         writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
 113         writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
 114         writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
 115         writel(2 << 22, &wdttimer->tcr);
 116         writel(0x0, &wdttimer->tim12);
 117         writel(0x0, &wdttimer->tim34);
 118         /* set WDEN bit, WDKEY 0xa5c6 */
 119         writel(0xa5c64000, &wdttimer->wdtcr);
 120         /* clear counter register */
 121         writel(0xda7e4000, &wdttimer->wdtcr);
 122 }
 123
 124 void davinci_hw_watchdog_reset(void)
 125 {
 126         writel(0xa5c64000, &wdttimer->wdtcr);
 127         writel(0xda7e4000, &wdttimer->wdtcr);
 128 }
 129 #endif