arch/arm/mach-bcm283x/init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2012 Stephen Warren
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <init.h>
  12 #include <dm/device.h>
  13 #include <fdt_support.h>
  14
  15 #ifdef CONFIG_ARM64
  16 #include <asm/armv8/mmu.h>
  17
  18 static struct mm_region bcm283x_mem_map[] = {
  19         {
  20                 .virt = 0x00000000UL,
  21                 .phys = 0x00000000UL,
  22                 .size = 0x3f000000UL,
  23                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  24                          PTE_BLOCK_INNER_SHARE
  25         }, {
  26                 .virt = 0x3f000000UL,
  27                 .phys = 0x3f000000UL,
  28                 .size = 0x01000000UL,
  29                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  30                          PTE_BLOCK_NON_SHARE |
  31                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  32         }, {
  33                 /* List terminator */
  34                 0,
  35         }
  36 };
  37
  38 static struct mm_region bcm2711_mem_map[] = {
  39         {
  40                 .virt = 0x00000000UL,
  41                 .phys = 0x00000000UL,
  42                 .size = 0xfe000000UL,
  43                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  44                          PTE_BLOCK_INNER_SHARE
  45         }, {
  46                 .virt = 0xfc000000UL,
  47                 .phys = 0xfc000000UL,
  48                 .size = 0x03800000UL,
  49                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  50                          PTE_BLOCK_NON_SHARE |
  51                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  52         }, {
  53                 /* List terminator */
  54                 0,
  55         }
  56 };
  57
  58 struct mm_region *mem_map = bcm283x_mem_map;
  59
  60 /*
  61  * I/O address space varies on different chip versions.
  62  * We set the base address by inspecting the DTB.
  63  */
  64 static const struct udevice_id board_ids[] = {
  65         { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
  66         { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
  67         { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
  68         { },
  69 };
  70
  71 static void _rpi_update_mem_map(struct mm_region *pd)
  72 {
  73         int i;
  74
  75         for (i = 0; i < 2; i++) {
  76                 mem_map[i].virt = pd[i].virt;
  77                 mem_map[i].phys = pd[i].phys;
  78                 mem_map[i].size = pd[i].size;
  79                 mem_map[i].attrs = pd[i].attrs;
  80         }
  81 }
  82
  83 static void rpi_update_mem_map(void)
  84 {
  85         int ret;
  86         struct mm_region *mm;
  87         const struct udevice_id *of_match = board_ids;
  88
  89         while (of_match->compatible) {
  90                 ret = fdt_node_check_compatible(gd->fdt_blob, 0,
  91                                                 of_match->compatible);
  92                 if (!ret) {
  93                         mm = (struct mm_region *)of_match->data;
  94                         _rpi_update_mem_map(mm);
  95                         break;
  96                 }
  97
  98                 of_match++;
  99         }
 100 }
 101 #else
 102 static void rpi_update_mem_map(void) {}
 103 #endif
 104
 105 unsigned long rpi_bcm283x_base = 0x3f000000;
 106
 107 int arch_cpu_init(void)
 108 {
 109         icache_enable();
 110
 111         return 0;
 112 }
 113
 114 int mach_cpu_init(void)
 115 {
 116         int ret, soc_offset;
 117         u64 io_base, size;
 118
 119         rpi_update_mem_map();
 120
 121         /* Get IO base from device tree */
 122         soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
 123         if (soc_offset < 0)
 124                 return soc_offset;
 125
 126         ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL,
 127                                 &io_base, &size);
 128         if (ret)
 129                 return ret;
 130
 131         rpi_bcm283x_base = io_base;
 132
 133         return 0;
 134 }
 135
 136 #ifdef CONFIG_ARMV7_LPAE
 137 void enable_caches(void)
 138 {
 139         dcache_enable();
 140 }
 141 #endif