arch/arm/mach-at91/armv7/clock.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
   4  *
   5  * Copyright (C) 2005 David Brownell
   6  * Copyright (C) 2005 Ivan Kokshaysky
   7  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   8  * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
   9  * Copyright (C) 2015 Wenyou Yang <wenyou.yang@atmel.com>
  10  */
  11
  12 #include <common.h>
  13 #include <linux/delay.h>
  14 #include <linux/errno.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/at91_pmc.h>
  18 #include <asm/arch/clk.h>
  19
  20 #if !defined(CONFIG_AT91FAMILY)
  21 # error You need to define CONFIG_AT91FAMILY in your board config!
  22 #endif
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 static unsigned long at91_css_to_rate(unsigned long css)
  27 {
  28         switch (css) {
  29         case AT91_PMC_MCKR_CSS_SLOW:
  30                 return CONFIG_SYS_AT91_SLOW_CLOCK;
  31         case AT91_PMC_MCKR_CSS_MAIN:
  32                 return gd->arch.main_clk_rate_hz;
  33         case AT91_PMC_MCKR_CSS_PLLA:
  34                 return gd->arch.plla_rate_hz;
  35         }
  36
  37         return 0;
  38 }
  39
  40 static u32 at91_pll_rate(u32 freq, u32 reg)
  41 {
  42         unsigned mul, div;
  43
  44         div = reg & 0xff;
  45         mul = (reg >> 18) & 0x7f;
  46         if (div && mul) {
  47                 freq /= div;
  48                 freq *= mul + 1;
  49         } else {
  50                 freq = 0;
  51         }
  52
  53         return freq;
  54 }
  55
  56 int at91_clock_init(unsigned long main_clock)
  57 {
  58         unsigned freq, mckr;
  59         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  60 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
  61         unsigned tmp;
  62         /*
  63          * When the bootloader initialized the main oscillator correctly,
  64          * there's no problem using the cycle counter.  But if it didn't,
  65          * or when using oscillator bypass mode, we must be told the speed
  66          * of the main clock.
  67          */
  68         if (!main_clock) {
  69                 do {
  70                         tmp = readl(&pmc->mcfr);
  71                 } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
  72                 tmp &= AT91_PMC_MCFR_MAINF_MASK;
  73                 main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
  74         }
  75 #endif
  76         gd->arch.main_clk_rate_hz = main_clock;
  77
  78         /* report if PLLA is more than mildly overclocked */
  79         gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
  80
  81         /*
  82          * MCK and CPU derive from one of those primary clocks.
  83          * For now, assume this parentage won't change.
  84          */
  85         mckr = readl(&pmc->mckr);
  86
  87         /* plla divisor by 2 */
  88         if (mckr & (1 << 12))
  89                 gd->arch.plla_rate_hz >>= 1;
  90
  91         gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
  92         freq = gd->arch.mck_rate_hz;
  93
  94         /* prescale */
  95         freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
  96
  97         switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
  98         case AT91_PMC_MCKR_MDIV_2:
  99                 gd->arch.mck_rate_hz = freq / 2;
 100                 break;
 101         case AT91_PMC_MCKR_MDIV_3:
 102                 gd->arch.mck_rate_hz = freq / 3;
 103                 break;
 104         case AT91_PMC_MCKR_MDIV_4:
 105                 gd->arch.mck_rate_hz = freq / 4;
 106                 break;
 107         default:
 108                 break;
 109         }
 110
 111         gd->arch.cpu_clk_rate_hz = freq;
 112
 113         return 0;
 114 }
 115
 116 void at91_plla_init(u32 pllar)
 117 {
 118         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 119
 120         writel(pllar, &pmc->pllar);
 121         while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
 122                 ;
 123 }
 124
 125 void at91_mck_init(u32 mckr)
 126 {
 127         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 128         u32 tmp;
 129
 130         tmp = readl(&pmc->mckr);
 131         tmp &= ~(AT91_PMC_MCKR_CSS_MASK  |
 132                  AT91_PMC_MCKR_PRES_MASK |
 133                  AT91_PMC_MCKR_MDIV_MASK |
 134                  AT91_PMC_MCKR_PLLADIV_2);
 135 #ifdef CPU_HAS_H32MXDIV
 136         tmp &= ~AT91_PMC_MCKR_H32MXDIV;
 137 #endif
 138
 139         tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK  |
 140                        AT91_PMC_MCKR_PRES_MASK |
 141                        AT91_PMC_MCKR_MDIV_MASK |
 142                        AT91_PMC_MCKR_PLLADIV_2);
 143 #ifdef CPU_HAS_H32MXDIV
 144         tmp |= mckr & AT91_PMC_MCKR_H32MXDIV;
 145 #endif
 146
 147         writel(tmp, &pmc->mckr);
 148
 149         while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
 150                 ;
 151 }
 152
 153 /*
 154  * For the Master Clock Controller Register(MCKR), while switching
 155  * to a lower clock source, we must switch the clock source first
 156  * instead of last. Otherwise, we could end up with too high frequency
 157  * on the internal bus and peripherals.
 158  */
 159 void at91_mck_init_down(u32 mckr)
 160 {
 161         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 162         u32 tmp;
 163
 164         tmp = readl(&pmc->mckr);
 165         tmp &= (~AT91_PMC_MCKR_CSS_MASK);
 166         tmp |= (mckr & AT91_PMC_MCKR_CSS_MASK);
 167         writel(tmp, &pmc->mckr);
 168
 169         while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
 170                 ;
 171
 172 #ifdef CPU_HAS_H32MXDIV
 173         tmp = readl(&pmc->mckr);
 174         tmp &= (~AT91_PMC_MCKR_H32MXDIV);
 175         tmp |= (mckr & AT91_PMC_MCKR_H32MXDIV);
 176         writel(tmp, &pmc->mckr);
 177 #endif
 178
 179         tmp = readl(&pmc->mckr);
 180         tmp &= (~AT91_PMC_MCKR_PLLADIV_MASK);
 181         tmp |= (mckr & AT91_PMC_MCKR_PLLADIV_MASK);
 182         writel(tmp, &pmc->mckr);
 183
 184         tmp = readl(&pmc->mckr);
 185         tmp &= (~AT91_PMC_MCKR_MDIV_MASK);
 186         tmp |= (mckr & AT91_PMC_MCKR_MDIV_MASK);
 187         writel(tmp, &pmc->mckr);
 188
 189         tmp = readl(&pmc->mckr);
 190         tmp &= (~AT91_PMC_MCKR_PRES_MASK);
 191         tmp |= (mckr & AT91_PMC_MCKR_PRES_MASK);
 192         writel(tmp, &pmc->mckr);
 193 }
 194
 195 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
 196 {
 197         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 198         u32 regval, status;
 199         u32 timeout = 1000;
 200
 201         if (id > AT91_PMC_PCR_PID_MASK)
 202                 return -EINVAL;
 203
 204         if (div > 0xff)
 205                 return -EINVAL;
 206
 207         if (clk_source == GCK_CSS_UPLL_CLK) {
 208                 if (at91_upll_clk_enable())
 209                         return -ENODEV;
 210         }
 211
 212         writel(id, &pmc->pcr);
 213         regval = readl(&pmc->pcr);
 214         regval &= ~AT91_PMC_PCR_GCKCSS;
 215         regval &= ~AT91_PMC_PCR_GCKDIV;
 216
 217         switch (clk_source) {
 218         case GCK_CSS_SLOW_CLK:
 219                 regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK;
 220                 break;
 221         case GCK_CSS_MAIN_CLK:
 222                 regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK;
 223                 break;
 224         case GCK_CSS_PLLA_CLK:
 225                 regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK;
 226                 break;
 227         case GCK_CSS_UPLL_CLK:
 228                 regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK;
 229                 break;
 230         case GCK_CSS_MCK_CLK:
 231                 regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK;
 232                 break;
 233         case GCK_CSS_AUDIO_CLK:
 234                 regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK;
 235                 break;
 236         default:
 237                 printf("Error GCK clock source selection!\n");
 238                 return -EINVAL;
 239         }
 240
 241         regval |= AT91_PMC_PCR_CMD_WRITE |
 242                   AT91_PMC_PCR_GCKDIV_(div) |
 243                   AT91_PMC_PCR_GCKEN;
 244
 245         writel(regval, &pmc->pcr);
 246
 247         do {
 248                 udelay(1);
 249                 status = readl(&pmc->sr);
 250         } while ((!!(--timeout)) && (!(status & AT91_PMC_GCKRDY)));
 251
 252         if (!timeout)
 253                 printf("Timeout waiting for GCK ready!\n");
 254
 255         return 0;
 256 }
 257
 258 u32 at91_get_periph_generated_clk(u32 id)
 259 {
 260         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 261         u32 regval, clk_source, div;
 262         u32 freq;
 263
 264         if (id > AT91_PMC_PCR_PID_MASK)
 265                 return 0;
 266
 267         writel(id, &pmc->pcr);
 268         regval = readl(&pmc->pcr);
 269
 270         clk_source = regval & AT91_PMC_PCR_GCKCSS;
 271         switch (clk_source) {
 272         case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
 273                 freq = CONFIG_SYS_AT91_SLOW_CLOCK;
 274                 break;
 275         case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
 276                 freq = gd->arch.main_clk_rate_hz;
 277                 break;
 278         case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
 279                 freq = gd->arch.plla_rate_hz;
 280                 break;
 281         case AT91_PMC_PCR_GCKCSS_UPLL_CLK:
 282                 freq = AT91_UTMI_PLL_CLK_FREQ;
 283                 break;
 284         case AT91_PMC_PCR_GCKCSS_MCK_CLK:
 285                 freq = gd->arch.mck_rate_hz;
 286                 break;
 287         default:
 288                 printf("Improper GCK clock source selection!\n");
 289                 freq = 0;
 290                 break;
 291         }
 292
 293         div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET);
 294         div += 1;
 295
 296         return freq / div;
 297 }