arch/arm/mach-at91/arm926ejs/lowlevel_init.S

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Memory Setup stuff - taken from blob memsetup.S
   4  *
   5  * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
   6  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
   7  *
   8  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
   9  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  10  */
  11
  12 #include <config.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/at91_pmc.h>
  15 #include <asm/arch/at91_wdt.h>
  16 #include <asm/arch/at91_pio.h>
  17 #include <asm/arch/at91_matrix.h>
  18 #include <asm/arch/at91sam9_sdramc.h>
  19 #include <asm/arch/at91sam9_smc.h>
  20 #include <asm/arch/at91_rstc.h>
  21 #ifdef CONFIG_ATMEL_LEGACY
  22 #include <asm/arch/at91sam9_matrix.h>
  23 #endif
  24 #ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
  25 #define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
  26 #endif
  27
  28 .globl lowlevel_init
  29 .type lowlevel_init,function
  30 lowlevel_init:
  31
  32 POS1:
  33         adr     r5, POS1        /* r5 = POS1 run time */
  34         ldr     r0, =POS1       /* r0 = POS1 compile */
  35         sub     r5, r5, r0      /* r0 = CONFIG_SYS_TEXT_BASE-1 */
  36
  37         /* memory control configuration 1 */
  38         ldr     r0, =SMRDATA
  39         ldr     r2, =SMRDATA1
  40         add     r0, r0, r5
  41         add     r2, r2, r5
  42 0:
  43         /* the address */
  44         ldr     r1, [r0], #4
  45         /* the value */
  46         ldr     r3, [r0], #4
  47         str     r3, [r1]
  48         cmp     r2, r0
  49         bne     0b
  50
  51 /* ----------------------------------------------------------------------------
  52  * PMC Init Step 1.
  53  * ----------------------------------------------------------------------------
  54  * - Check if the PLL is already initialized
  55  * ----------------------------------------------------------------------------
  56  */
  57         ldr     r1, =(AT91_ASM_PMC_MCKR)
  58         ldr     r0, [r1]
  59         and     r0, r0, #3
  60         cmp     r0, #0
  61         bne     PLL_setup_end
  62
  63 /* ---------------------------------------------------------------------------
  64  * - Enable the Main Oscillator
  65  * ---------------------------------------------------------------------------
  66  */
  67         ldr     r1, =(AT91_ASM_PMC_MOR)
  68         ldr     r2, =(AT91_ASM_PMC_SR)
  69         /* Main oscillator Enable register PMC_MOR: */
  70         ldr     r0, =CONFIG_SYS_MOR_VAL
  71         str     r0, [r1]
  72
  73         /* Reading the PMC Status to detect when the Main Oscillator is enabled */
  74         mov     r4, #AT91_PMC_IXR_MOSCS
  75 MOSCS_Loop:
  76         ldr     r3, [r2]
  77         and     r3, r4, r3
  78         cmp     r3, #AT91_PMC_IXR_MOSCS
  79         bne     MOSCS_Loop
  80
  81 /* ----------------------------------------------------------------------------
  82  * PMC Init Step 2.
  83  * ----------------------------------------------------------------------------
  84  * Setup PLLA
  85  * ----------------------------------------------------------------------------
  86  */
  87         ldr     r1, =(AT91_ASM_PMC_PLLAR)
  88         ldr     r0, =CONFIG_SYS_PLLAR_VAL
  89         str     r0, [r1]
  90
  91         /* Reading the PMC Status register to detect when the PLLA is locked */
  92         mov     r4, #AT91_PMC_IXR_LOCKA
  93 MOSCS_Loop1:
  94         ldr     r3, [r2]
  95         and     r3, r4, r3
  96         cmp     r3, #AT91_PMC_IXR_LOCKA
  97         bne     MOSCS_Loop1
  98
  99 /* ----------------------------------------------------------------------------
 100  * PMC Init Step 3.
 101  * ----------------------------------------------------------------------------
 102  * - Switch on the Main Oscillator
 103  * ----------------------------------------------------------------------------
 104  */
 105         ldr     r1, =(AT91_ASM_PMC_MCKR)
 106
 107         /* -Master Clock Controller register PMC_MCKR */
 108         ldr     r0, =CONFIG_SYS_MCKR1_VAL
 109         str     r0, [r1]
 110
 111         /* Reading the PMC Status to detect when the Master clock is ready */
 112         mov     r4, #AT91_PMC_IXR_MCKRDY
 113 MCKRDY_Loop:
 114         ldr     r3, [r2]
 115         and     r3, r4, r3
 116         cmp     r3, #AT91_PMC_IXR_MCKRDY
 117         bne     MCKRDY_Loop
 118
 119         ldr     r0, =CONFIG_SYS_MCKR2_VAL
 120         str     r0, [r1]
 121
 122         /* Reading the PMC Status to detect when the Master clock is ready */
 123         mov     r4, #AT91_PMC_IXR_MCKRDY
 124 MCKRDY_Loop1:
 125         ldr     r3, [r2]
 126         and     r3, r4, r3
 127         cmp     r3, #AT91_PMC_IXR_MCKRDY
 128         bne     MCKRDY_Loop1
 129 PLL_setup_end:
 130
 131 /* ----------------------------------------------------------------------------
 132  * - memory control configuration 2
 133  * ----------------------------------------------------------------------------
 134  */
 135         ldr     r0, =(AT91_ASM_SDRAMC_TR)
 136         ldr     r1, [r0]
 137         cmp     r1, #0
 138         bne     SDRAM_setup_end
 139
 140         ldr     r0, =SMRDATA1
 141         ldr     r2, =SMRDATA2
 142         add     r0, r0, r5
 143         add     r2, r2, r5
 144 2:
 145         /* the address */
 146         ldr     r1, [r0], #4
 147         /* the value */
 148         ldr     r3, [r0], #4
 149         str     r3, [r1]
 150         cmp     r2, r0
 151         bne     2b
 152
 153 SDRAM_setup_end:
 154         /* everything is fine now */
 155         mov     pc, lr
 156
 157         .ltorg
 158
 159 SMRDATA:
 160         .word AT91_ASM_WDT_MR
 161         .word CONFIG_SYS_WDTC_WDMR_VAL
 162         /* configure PIOx as EBI0 D[16-31] */
 163 #if defined(CONFIG_AT91SAM9263)
 164         .word AT91_ASM_PIOD_PDR
 165         .word CONFIG_SYS_PIOD_PDR_VAL1
 166         .word AT91_ASM_PIOD_PUDR
 167         .word CONFIG_SYS_PIOD_PPUDR_VAL
 168         .word AT91_ASM_PIOD_ASR
 169         .word CONFIG_SYS_PIOD_PPUDR_VAL
 170 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
 171         || defined(CONFIG_AT91SAM9G20)
 172         .word AT91_ASM_PIOC_PDR
 173         .word CONFIG_SYS_PIOC_PDR_VAL1
 174         .word AT91_ASM_PIOC_PUDR
 175         .word CONFIG_SYS_PIOC_PPUDR_VAL
 176 #endif
 177         .word AT91_ASM_MATRIX_CSA0
 178         .word CONFIG_SYS_MATRIX_EBICSA_VAL
 179
 180         /* flash */
 181         .word AT91_ASM_SMC_MODE0
 182         .word CONFIG_SYS_SMC0_MODE0_VAL
 183
 184         .word AT91_ASM_SMC_CYCLE0
 185         .word CONFIG_SYS_SMC0_CYCLE0_VAL
 186
 187         .word AT91_ASM_SMC_PULSE0
 188         .word CONFIG_SYS_SMC0_PULSE0_VAL
 189
 190         .word AT91_ASM_SMC_SETUP0
 191         .word CONFIG_SYS_SMC0_SETUP0_VAL
 192
 193 SMRDATA1:
 194         .word AT91_ASM_SDRAMC_MR
 195         .word CONFIG_SYS_SDRC_MR_VAL1
 196         .word AT91_ASM_SDRAMC_TR
 197         .word CONFIG_SYS_SDRC_TR_VAL1
 198         .word AT91_ASM_SDRAMC_CR
 199         .word CONFIG_SYS_SDRC_CR_VAL
 200         .word AT91_ASM_SDRAMC_MDR
 201         .word CONFIG_SYS_SDRC_MDR_VAL
 202         .word AT91_ASM_SDRAMC_MR
 203         .word CONFIG_SYS_SDRC_MR_VAL2
 204         .word CONFIG_SYS_SDRAM_BASE
 205         .word CONFIG_SYS_SDRAM_VAL1
 206         .word AT91_ASM_SDRAMC_MR
 207         .word CONFIG_SYS_SDRC_MR_VAL3
 208         .word CONFIG_SYS_SDRAM_BASE
 209         .word CONFIG_SYS_SDRAM_VAL2
 210         .word CONFIG_SYS_SDRAM_BASE
 211         .word CONFIG_SYS_SDRAM_VAL3
 212         .word CONFIG_SYS_SDRAM_BASE
 213         .word CONFIG_SYS_SDRAM_VAL4
 214         .word CONFIG_SYS_SDRAM_BASE
 215         .word CONFIG_SYS_SDRAM_VAL5
 216         .word CONFIG_SYS_SDRAM_BASE
 217         .word CONFIG_SYS_SDRAM_VAL6
 218         .word CONFIG_SYS_SDRAM_BASE
 219         .word CONFIG_SYS_SDRAM_VAL7
 220         .word CONFIG_SYS_SDRAM_BASE
 221         .word CONFIG_SYS_SDRAM_VAL8
 222         .word CONFIG_SYS_SDRAM_BASE
 223         .word CONFIG_SYS_SDRAM_VAL9
 224         .word AT91_ASM_SDRAMC_MR
 225         .word CONFIG_SYS_SDRC_MR_VAL4
 226         .word CONFIG_SYS_SDRAM_BASE
 227         .word CONFIG_SYS_SDRAM_VAL10
 228         .word AT91_ASM_SDRAMC_MR
 229         .word CONFIG_SYS_SDRC_MR_VAL5
 230         .word CONFIG_SYS_SDRAM_BASE
 231         .word CONFIG_SYS_SDRAM_VAL11
 232         .word AT91_ASM_SDRAMC_TR
 233         .word CONFIG_SYS_SDRC_TR_VAL2
 234         .word CONFIG_SYS_SDRAM_BASE
 235         .word CONFIG_SYS_SDRAM_VAL12
 236         /* User reset enable*/
 237         .word AT91_ASM_RSTC_MR
 238         .word CONFIG_SYS_RSTC_RMR_VAL
 239 #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
 240         /* MATRIX_MCFG - REMAP all masters */
 241         .word AT91_ASM_MATRIX_MCFG
 242         .word 0x1FF
 243 #endif
 244 SMRDATA2:
 245         .word 0