2 * Sunxi platform display controller register and constant defines
4 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _SUNXI_DISPLAY_H
10 #define _SUNXI_DISPLAY_H
12 struct sunxi_de_be_reg {
13 u8 res0[0x800]; /* 0x000 */
15 u32 backcolor; /* 0x804 */
16 u32 disp_size; /* 0x808 */
17 u8 res1[0x4]; /* 0x80c */
18 u32 layer0_size; /* 0x810 */
19 u32 layer1_size; /* 0x814 */
20 u32 layer2_size; /* 0x818 */
21 u32 layer3_size; /* 0x81c */
22 u32 layer0_pos; /* 0x820 */
23 u32 layer1_pos; /* 0x824 */
24 u32 layer2_pos; /* 0x828 */
25 u32 layer3_pos; /* 0x82c */
26 u8 res2[0x10]; /* 0x830 */
27 u32 layer0_stride; /* 0x840 */
28 u32 layer1_stride; /* 0x844 */
29 u32 layer2_stride; /* 0x848 */
30 u32 layer3_stride; /* 0x84c */
31 u32 layer0_addr_low32b; /* 0x850 */
32 u32 layer1_addr_low32b; /* 0x854 */
33 u32 layer2_addr_low32b; /* 0x858 */
34 u32 layer3_addr_low32b; /* 0x85c */
35 u32 layer0_addr_high4b; /* 0x860 */
36 u32 layer1_addr_high4b; /* 0x864 */
37 u32 layer2_addr_high4b; /* 0x868 */
38 u32 layer3_addr_high4b; /* 0x86c */
39 u32 reg_ctrl; /* 0x870 */
40 u8 res3[0xc]; /* 0x874 */
41 u32 color_key_max; /* 0x880 */
42 u32 color_key_min; /* 0x884 */
43 u32 color_key_config; /* 0x888 */
44 u8 res4[0x4]; /* 0x88c */
45 u32 layer0_attr0_ctrl; /* 0x890 */
46 u32 layer1_attr0_ctrl; /* 0x894 */
47 u32 layer2_attr0_ctrl; /* 0x898 */
48 u32 layer3_attr0_ctrl; /* 0x89c */
49 u32 layer0_attr1_ctrl; /* 0x8a0 */
50 u32 layer1_attr1_ctrl; /* 0x8a4 */
51 u32 layer2_attr1_ctrl; /* 0x8a8 */
52 u32 layer3_attr1_ctrl; /* 0x8ac */
55 struct sunxi_lcdc_reg {
59 u8 res0[0x04]; /* 0x0c */
60 u32 tcon0_frm_ctrl; /* 0x10 */
61 u32 tcon0_frm_seed[6]; /* 0x14 */
62 u32 tcon0_frm_table[4]; /* 0x2c */
63 u8 res1[4]; /* 0x3c */
64 u32 tcon0_ctrl; /* 0x40 */
65 u32 tcon0_dclk; /* 0x44 */
66 u32 tcon0_timing_active; /* 0x48 */
67 u32 tcon0_timing_h; /* 0x4c */
68 u32 tcon0_timing_v; /* 0x50 */
69 u32 tcon0_timing_sync; /* 0x54 */
70 u32 tcon0_hv_intf; /* 0x58 */
71 u8 res2[0x04]; /* 0x5c */
72 u32 tcon0_cpu_intf; /* 0x60 */
73 u32 tcon0_cpu_wr_dat; /* 0x64 */
74 u32 tcon0_cpu_rd_dat0; /* 0x68 */
75 u32 tcon0_cpu_rd_dat1; /* 0x6c */
76 u32 tcon0_ttl_timing0; /* 0x70 */
77 u32 tcon0_ttl_timing1; /* 0x74 */
78 u32 tcon0_ttl_timing2; /* 0x78 */
79 u32 tcon0_ttl_timing3; /* 0x7c */
80 u32 tcon0_ttl_timing4; /* 0x80 */
81 u32 tcon0_lvds_intf; /* 0x84 */
82 u32 tcon0_io_polarity; /* 0x88 */
83 u32 tcon0_io_tristate; /* 0x8c */
84 u32 tcon1_ctrl; /* 0x90 */
85 u32 tcon1_timing_source; /* 0x94 */
86 u32 tcon1_timing_scale; /* 0x98 */
87 u32 tcon1_timing_out; /* 0x9c */
88 u32 tcon1_timing_h; /* 0xa0 */
89 u32 tcon1_timing_v; /* 0xa4 */
90 u32 tcon1_timing_sync; /* 0xa8 */
91 u8 res3[0x44]; /* 0xac */
92 u32 tcon1_io_polarity; /* 0xf0 */
93 u32 tcon1_io_tristate; /* 0xf4 */
94 u8 res4[0x128]; /* 0xf8 */
95 u32 lvds_ana0; /* 0x220 */
96 u32 lvds_ana1; /* 0x224 */
99 struct sunxi_hdmi_reg {
100 u32 version_id; /* 0x000 */
101 u32 ctrl; /* 0x004 */
104 u32 video_ctrl; /* 0x010 */
105 u32 video_size; /* 0x014 */
106 u32 video_bp; /* 0x018 */
107 u32 video_fp; /* 0x01c */
108 u32 video_spw; /* 0x020 */
109 u32 video_polarity; /* 0x024 */
110 u8 res0[0x58]; /* 0x028 */
111 u8 avi_info_frame[0x14]; /* 0x080 */
112 u8 res1[0x4c]; /* 0x094 */
113 u32 qcp_packet0; /* 0x0e0 */
114 u32 qcp_packet1; /* 0x0e4 */
115 u8 res2[0x118]; /* 0x0e8 */
116 u32 pad_ctrl0; /* 0x200 */
117 u32 pad_ctrl1; /* 0x204 */
118 u32 pll_ctrl; /* 0x208 */
119 u32 pll_dbg0; /* 0x20c */
120 u32 pll_dbg1; /* 0x210 */
121 u32 hpd_cec; /* 0x214 */
122 u8 res3[0x28]; /* 0x218 */
123 u8 vendor_info_frame[0x14]; /* 0x240 */
124 u8 res4[0x9c]; /* 0x254 */
125 u32 pkt_ctrl0; /* 0x2f0 */
126 u32 pkt_ctrl1; /* 0x2f4 */
127 u8 res5[0x8]; /* 0x2f8 */
128 u32 unknown; /* 0x300 */
129 u8 res6[0xc]; /* 0x304 */
130 u32 audio_sample_count; /* 0x310 */
131 u8 res7[0xec]; /* 0x314 */
132 u32 audio_tx_fifo; /* 0x400 */
133 u8 res8[0xfc]; /* 0x404 */
134 #ifndef CONFIG_MACH_SUN6I
135 u32 ddc_ctrl; /* 0x500 */
136 u32 ddc_addr; /* 0x504 */
137 u32 ddc_int_mask; /* 0x508 */
138 u32 ddc_int_status; /* 0x50c */
139 u32 ddc_fifo_ctrl; /* 0x510 */
140 u32 ddc_fifo_status; /* 0x514 */
141 u32 ddc_fifo_data; /* 0x518 */
142 u32 ddc_byte_count; /* 0x51c */
143 u32 ddc_cmnd; /* 0x520 */
144 u32 ddc_exreg; /* 0x524 */
145 u32 ddc_clock; /* 0x528 */
146 u8 res9[0x14]; /* 0x52c */
147 u32 ddc_line_ctrl; /* 0x540 */
149 u32 ddc_ctrl; /* 0x500 */
150 u32 ddc_exreg; /* 0x504 */
151 u32 ddc_cmnd; /* 0x508 */
152 u32 ddc_addr; /* 0x50c */
153 u32 ddc_int_mask; /* 0x510 */
154 u32 ddc_int_status; /* 0x514 */
155 u32 ddc_fifo_ctrl; /* 0x518 */
156 u32 ddc_fifo_status; /* 0x51c */
157 u32 ddc_clock; /* 0x520 */
158 u32 ddc_timeout; /* 0x524 */
159 u8 res9[0x18]; /* 0x528 */
160 u32 ddc_dbg; /* 0x540 */
161 u8 res10[0x3c]; /* 0x544 */
162 u32 ddc_fifo_data; /* 0x580 */
167 * This is based on the A10s User Manual, and the A10s only supports
168 * composite video and not vga like the A10 / A20 does, still other
169 * than the removed vga out capability the tvencoder seems to be the same.
170 * "unknown#" registers are registers which are used in the A10 kernel code,
171 * but not documented in the A10s User Manual.
173 struct sunxi_tve_reg {
174 u32 gctrl; /* 0x000 */
175 u32 cfg0; /* 0x004 */
176 u32 dac_cfg0; /* 0x008 */
177 u32 filter; /* 0x00c */
178 u32 chroma_freq; /* 0x010 */
179 u32 porch_num; /* 0x014 */
180 u32 unknown0; /* 0x018 */
181 u32 line_num; /* 0x01c */
182 u32 blank_black_level; /* 0x020 */
183 u32 unknown1; /* 0x024, seems to be 1 byte per dac */
184 u8 res0[0x08]; /* 0x028 */
185 u32 auto_detect_en; /* 0x030 */
186 u32 auto_detect_int_status; /* 0x034 */
187 u32 auto_detect_status; /* 0x038 */
188 u32 auto_detect_debounce; /* 0x03c */
189 u32 csc_reg0; /* 0x040 */
190 u32 csc_reg1; /* 0x044 */
191 u32 csc_reg2; /* 0x048 */
192 u32 csc_reg3; /* 0x04c */
193 u8 res1[0xb0]; /* 0x050 */
194 u32 color_burst; /* 0x100 */
195 u32 vsync_num; /* 0x104 */
196 u32 notch_freq; /* 0x108 */
197 u32 cbr_level; /* 0x10c */
198 u32 burst_phase; /* 0x110 */
199 u32 burst_width; /* 0x114 */
200 u8 res2[0x04]; /* 0x118 */
201 u32 sync_vbi_level; /* 0x11c */
202 u32 white_level; /* 0x120 */
203 u32 active_num; /* 0x124 */
204 u32 chroma_bw_gain; /* 0x128 */
205 u32 notch_width; /* 0x12c */
206 u32 resync_num; /* 0x130 */
207 u32 slave_para; /* 0x134 */
208 u32 cfg1; /* 0x138 */
209 u32 cfg2; /* 0x13c */
213 * DE-BE register constants.
215 #define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0)
216 #define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16)
217 #define SUNXI_DE_BE_MODE_ENABLE (1 << 0)
218 #define SUNXI_DE_BE_MODE_START (1 << 1)
219 #define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8)
220 #define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5)
221 #define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0)
222 #define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
225 * LCDC register constants.
227 #define SUNXI_LCDC_X(x) (((x) - 1) << 16)
228 #define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
229 #define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
230 #define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
231 #define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
232 #define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
233 #define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
234 #define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
235 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4))
236 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4))
237 #define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111
238 #define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000
239 #define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111
240 #define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555
241 #define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777
242 #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
243 #define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31)
244 #define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0)
245 #define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
246 #define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0)
247 #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
248 #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0)
249 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
250 #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26)
251 #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31)
252 #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0 (0 << 28)
253 #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60 (1 << 28)
254 #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE120 (2 << 28)
255 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
256 #define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
257 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
258 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
259 #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
260 #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16)
261 #define SUNXI_LCDC_LVDS_ANA0 0x3f310000
262 #define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22)
263 #define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10)
264 #define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00)
267 * HDMI register constants.
269 #define SUNXI_HDMI_X(x) (((x) - 1) << 0)
270 #define SUNXI_HDMI_Y(y) (((y) - 1) << 16)
271 #define SUNXI_HDMI_CTRL_ENABLE (1 << 31)
272 #define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0)
273 #define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1)
274 #define SUNXI_HDMI_IRQ_STATUS_BITS 0x73
275 #define SUNXI_HDMI_HPD_DETECT (1 << 0)
276 #define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31)
277 #define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30)
278 #define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0)
279 #define SUNXI_HDMI_VIDEO_POL_VER (1 << 1)
280 #define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16)
281 #define SUNXI_HDMI_QCP_PACKET0 3
282 #define SUNXI_HDMI_QCP_PACKET1 0
284 #ifdef CONFIG_MACH_SUN6I
285 #define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f
286 #define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff
288 #define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000
289 #define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000
292 #ifdef CONFIG_MACH_SUN4I
293 #define SUNXI_HDMI_PAD_CTRL1 0x00d8c820
294 #elif defined CONFIG_MACH_SUN6I
295 #define SUNXI_HDMI_PAD_CTRL1 0x01ded030
297 #define SUNXI_HDMI_PAD_CTRL1 0x00d8c830
299 #define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6)
301 #ifdef CONFIG_MACH_SUN6I
302 #define SUNXI_HDMI_PLL_CTRL 0xba48a308
303 #define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4)
305 #define SUNXI_HDMI_PLL_CTRL 0xfa4ef708
306 #define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4)
308 #define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4)
310 #define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21)
311 #define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21)
313 #define SUNXI_HDMI_PKT_CTRL0 0x00000f21
314 #define SUNXI_HDMI_PKT_CTRL1 0x0000000f
315 #define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000
317 #ifdef CONFIG_MACH_SUN6I
318 #define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0)
319 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4)
320 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6)
321 #define SUNXI_HMDI_DDC_CTRL_START (1 << 27)
322 #define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31)
324 #define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0)
325 /* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */
326 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0
327 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0
328 #define SUNXI_HMDI_DDC_CTRL_START (1 << 30)
329 #define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31)
332 #ifdef CONFIG_MACH_SUN6I
333 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0)
335 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0)
337 #define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8)
338 #define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16)
339 #define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24)
341 #ifdef CONFIG_MACH_SUN6I
342 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15)
344 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31)
347 #define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6
348 #define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7
350 #ifdef CONFIG_MACH_SUN6I
351 #define SUNXI_HDMI_DDC_CLOCK 0x61
353 /* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */
354 #define SUNXI_HDMI_DDC_CLOCK 0x0d
357 #define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8)
358 #define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9)
361 * TVE register constants.
363 #define SUNXI_TVE_GCTRL_ENABLE (1 << 0)
365 * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed
366 * dac from tve1. When using tve1 the mux value must be written to both tve0's
367 * and tve1's gctrl reg.
369 #define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4))
370 #define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4))
371 #define SUNXI_TVE_GCTRL_CFG0_VGA 0x20000000
372 #define SUNXI_TVE_GCTRL_DAC_CFG0_VGA 0x403e1ac7
373 #define SUNXI_TVE_GCTRL_UNKNOWN1_VGA 0x00000000
374 #define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0))
375 #define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16))
376 #define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0))
377 #define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8)
378 #define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8))
379 #define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0
380 #define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1
381 #define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3
382 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8)
383 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8))
384 #define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31)
385 #define SUNXI_TVE_CSC_REG0 0x08440832
386 #define SUNXI_TVE_CSC_REG1 0x3b6dace1
387 #define SUNXI_TVE_CSC_REG2 0x0e1d13dc
388 #define SUNXI_TVE_CSC_REG3 0x00108080
390 int sunxi_simplefb_setup(void *blob);
392 #endif /* _SUNXI_DISPLAY_H */
projects / oweals / u-boot.git / blob