arch/arm/include/asm/arch-s32v234/imx-regs.h

   1 /*
   2  * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ASM_ARCH_IMX_REGS_H__
   8 #define __ASM_ARCH_IMX_REGS_H__
   9
  10 #define ARCH_MXC
  11
  12 #define IRAM_BASE_ADDR      0x3E800000  /* internal ram */
  13 #define IRAM_SIZE           0x00400000  /* 4MB */
  14
  15 #define AIPS0_BASE_ADDR     (0x40000000UL)
  16 #define AIPS1_BASE_ADDR     (0x40080000UL)
  17
  18 /* AIPS 0 */
  19 #define AXBS_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00000000)
  20 #define CSE3_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00001000)
  21 #define EDMA_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00002000)
  22 #define XRDC_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00004000)
  23 #define SWT0_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x0000A000)
  24 #define SWT1_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x0000B000)
  25 #define STM0_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x0000D000)
  26 #define NIC301_BASE_ADDR                                (AIPS0_BASE_ADDR + 0x00010000)
  27 #define GC3000_BASE_ADDR                                (AIPS0_BASE_ADDR + 0x00020000)
  28 #define DEC200_DECODER_BASE_ADDR                (AIPS0_BASE_ADDR + 0x00026000)
  29 #define DEC200_ENCODER_BASE_ADDR                (AIPS0_BASE_ADDR + 0x00027000)
  30 #define TWOD_ACE_BASE_ADDR                              (AIPS0_BASE_ADDR + 0x00028000)
  31 #define MIPI_CSI0_BASE_ADDR                             (AIPS0_BASE_ADDR + 0x00030000)
  32 #define DMAMUX0_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x00031000)
  33 #define ENET_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00032000)
  34 #define FLEXRAY_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x00034000)
  35 #define MMDC0_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00036000)
  36 #define MEW0_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00037000)
  37 #define MONITOR_DDR0_BASE_ADDR                  (AIPS0_BASE_ADDR + 0x00038000)
  38 #define MONITOR_CCI0_BASE_ADDR                  (AIPS0_BASE_ADDR + 0x00039000)
  39 #define PIT0_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x0003A000)
  40 #define MC_CGM0_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x0003C000)
  41 #define MC_CGM1_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x0003F000)
  42 #define MC_CGM2_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x00042000)
  43 #define MC_CGM3_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x00045000)
  44 #define MC_RGM_BASE_ADDR                                (AIPS0_BASE_ADDR + 0x00048000)
  45 #define MC_ME_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x0004A000)
  46 #define MC_PCU_BASE_ADDR                                (AIPS0_BASE_ADDR + 0x0004B000)
  47 #define ADC0_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x0004D000)
  48 #define FLEXTIMER_BASE_ADDR                             (AIPS0_BASE_ADDR + 0x0004F000)
  49 #define I2C0_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00051000)
  50 #define LINFLEXD0_BASE_ADDR                             (AIPS0_BASE_ADDR + 0x00053000)
  51 #define FLEXCAN0_BASE_ADDR                              (AIPS0_BASE_ADDR + 0x00055000)
  52 #define SPI0_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00057000)
  53 #define SPI2_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00059000)
  54 #define CRC0_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x0005B000)
  55 #define USDHC_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x0005D000)
  56 #define OCOTP_CONTROLLER_BASE_ADDR              (AIPS0_BASE_ADDR + 0x0005F000)
  57 #define WKPU_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00063000)
  58 #define VIU0_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00064000)
  59 #define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000)
  60 #define SIUL2_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x0006C000)
  61 #define SIPI_BASE_ADDR                                  (AIPS0_BASE_ADDR + 0x00074000)
  62 #define LFAST_BASE_ADDR                                 (AIPS0_BASE_ADDR + 0x00078000)
  63 #define SSE_BASE_ADDR                                   (AIPS0_BASE_ADDR + 0x00079000)
  64 #define SRC_SOC_BASE_ADDR                               (AIPS0_BASE_ADDR + 0x0007C000)
  65
  66 /* AIPS 1 */
  67 #define ERM_BASE_ADDR                                   (AIPS1_BASE_ADDR + 0X000000000)
  68 #define MSCM_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000001000)
  69 #define SEMA42_BASE_ADDR                                (AIPS1_BASE_ADDR + 0X000002000)
  70 #define INTC_MON_BASE_ADDR                              (AIPS1_BASE_ADDR + 0X000003000)
  71 #define SWT2_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000004000)
  72 #define SWT3_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000005000)
  73 #define SWT4_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000006000)
  74 #define STM1_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000007000)
  75 #define EIM_BASE_ADDR                                   (AIPS1_BASE_ADDR + 0X000008000)
  76 #define APB_BASE_ADDR                                   (AIPS1_BASE_ADDR + 0X000009000)
  77 #define XBIC_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000012000)
  78 #define MIPI_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000020000)
  79 #define DMAMUX1_BASE_ADDR                               (AIPS1_BASE_ADDR + 0X000021000)
  80 #define MMDC1_BASE_ADDR                                 (AIPS1_BASE_ADDR + 0X000022000)
  81 #define MEW1_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000023000)
  82 #define DDR1_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000024000)
  83 #define CCI1_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000025000)
  84 #define QUADSPI0_BASE_ADDR                              (AIPS1_BASE_ADDR + 0X000026000)
  85 #define PIT1_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X00002A000)
  86 #define FCCU_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000030000)
  87 #define FLEXTIMER_FTM1_BASE_ADDR                (AIPS1_BASE_ADDR + 0X000036000)
  88 #define I2C1_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000038000)
  89 #define I2C2_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X00003A000)
  90 #define LINFLEXD1_BASE_ADDR                             (AIPS1_BASE_ADDR + 0X00003C000)
  91 #define FLEXCAN1_BASE_ADDR                              (AIPS1_BASE_ADDR + 0X00003E000)
  92 #define SPI1_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000040000)
  93 #define SPI3_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000042000)
  94 #define IPL_BASE_ADDR                                   (AIPS1_BASE_ADDR + 0X000043000)
  95 #define CGM_CMU_BASE_ADDR                               (AIPS1_BASE_ADDR + 0X000044000)
  96 #define PMC_BASE_ADDR                                   (AIPS1_BASE_ADDR + 0X000048000)
  97 #define CRC1_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X00004C000)
  98 #define TMU_BASE_ADDR                                   (AIPS1_BASE_ADDR + 0X00004E000)
  99 #define VIU1_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000050000)
 100 #define JPEG_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000054000)
 101 #define H264_DEC_BASE_ADDR                              (AIPS1_BASE_ADDR + 0X000058000)
 102 #define H264_ENC_BASE_ADDR                              (AIPS1_BASE_ADDR + 0X00005C000)
 103 #define MEMU_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000060000)
 104 #define STCU_BASE_ADDR                                  (AIPS1_BASE_ADDR + 0X000064000)
 105 #define SLFTST_CTRL_BASE_ADDR                   (AIPS1_BASE_ADDR + 0X000066000)
 106 #define MCT_BASE_ADDR                                   (AIPS1_BASE_ADDR + 0X000068000)
 107 #define REP_BASE_ADDR                                   (AIPS1_BASE_ADDR + 0X00006A000)
 108 #define MBIST_CONTROLLER_BASE_ADDR              (AIPS1_BASE_ADDR + 0X00006C000)
 109 #define BOOT_LOADER_BASE_ADDR                   (AIPS1_BASE_ADDR + 0X00006F000)
 110
 111 /* TODO Remove this after the IOMUX framework is implemented */
 112 #define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
 113
 114 /* MUX mode and PAD ctrl are in one register */
 115 #define CONFIG_IOMUX_SHARE_CONF_REG
 116
 117 #define FEC_QUIRK_ENET_MAC
 118 #define I2C_QUIRK_REG
 119
 120 /* MSCM interrupt router */
 121 #define MSCM_IRSPRC_CPn_EN              3
 122 #define MSCM_IRSPRC_NUM                 176
 123 #define MSCM_CPXTYPE_RYPZ_MASK          0xFF
 124 #define MSCM_CPXTYPE_RYPZ_OFFSET        0
 125 #define MSCM_CPXTYPE_PERS_MASK          0xFFFFFF00
 126 #define MSCM_CPXTYPE_PERS_OFFSET        8
 127 #define MSCM_CPXTYPE_PERS_A53           0x413533
 128 #define MSCM_CPXTYPE_PERS_CM4           0x434d34
 129
 130 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 131 #include <asm/types.h>
 132
 133 /* System Reset Controller (SRC) */
 134 struct src {
 135         u32 bmr1;
 136         u32 bmr2;
 137         u32 gpr1_boot;
 138         u32 reserved_0x00C[61];
 139         u32 gpr1;
 140         u32 gpr2;
 141         u32 gpr3;
 142         u32 gpr4;
 143         u32 gpr5;
 144         u32 gpr6;
 145         u32 gpr7;
 146         u32 reserved_0x11C[1];
 147         u32 gpr9;
 148         u32 gpr10;
 149         u32 gpr11;
 150         u32 gpr12;
 151         u32 gpr13;
 152         u32 gpr14;
 153         u32 gpr15;
 154         u32 gpr16;
 155         u32 reserved_0x140[1];
 156         u32 gpr17;
 157         u32 gpr18;
 158         u32 gpr19;
 159         u32 gpr20;
 160         u32 gpr21;
 161         u32 gpr22;
 162         u32 gpr23;
 163         u32 gpr24;
 164         u32 gpr25;
 165         u32 gpr26;
 166         u32 gpr27;
 167         u32 reserved_0x16C[5];
 168         u32 pcie_config1;
 169         u32 ddr_self_ref_ctrl;
 170         u32 pcie_config0;
 171         u32 reserved_0x18C[4];
 172         u32 soc_misc_config2;
 173 };
 174
 175 /* SRC registers definitions */
 176
 177 /* SRC_GPR1 */
 178 #define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
 179                                                                                 (SRC_GPR1_PLL_OFFSET + (pll)) )
 180 #define SRC_GPR1_PLL_SOURCE_MASK        (0x1)
 181
 182 #define SRC_GPR1_PLL_OFFSET                     (27)
 183 #define SRC_GPR1_FIRC_CLK_SOURCE        (0x0)
 184 #define SRC_GPR1_XOSC_CLK_SOURCE        (0x1)
 185
 186 /* Periodic Interrupt Timer (PIT) */
 187 struct pit_reg {
 188         u32 mcr;
 189         u32 recv0[55];
 190         u32 ltmr64h;
 191         u32 ltmr64l;
 192         u32 recv1[6];
 193         u32 ldval0;
 194         u32 cval0;
 195         u32 tctrl0;
 196         u32 tflg0;
 197         u32 ldval1;
 198         u32 cval1;
 199         u32 tctrl1;
 200         u32 tflg1;
 201         u32 ldval2;
 202         u32 cval2;
 203         u32 tctrl2;
 204         u32 tflg2;
 205         u32 ldval3;
 206         u32 cval3;
 207         u32 tctrl3;
 208         u32 tflg3;
 209         u32 ldval4;
 210         u32 cval4;
 211         u32 tctrl4;
 212         u32 tflg4;
 213         u32 ldval5;
 214         u32 cval5;
 215         u32 tctrl5;
 216         u32 tflg5;
 217 };
 218
 219 /* Watchdog Timer (WDOG) */
 220 struct wdog_regs {
 221         u32 cr;
 222         u32 ir;
 223         u32 to;
 224         u32 wn;
 225         u32 sr;
 226         u32 co;
 227         u32 sk;
 228 };
 229
 230 /* UART */
 231 struct linflex_fsl {
 232         u32 lincr1;
 233         u32 linier;
 234         u32 linsr;
 235         u32 linesr;
 236         u32 uartcr;
 237         u32 uartsr;
 238         u32 lintcsr;
 239         u32 linocr;
 240         u32 lintocr;
 241         u32 linfbrr;
 242         u32 linibrr;
 243         u32 lincfr;
 244         u32 lincr2;
 245         u32 bidr;
 246         u32 bdrl;
 247         u32 bdrm;
 248         u32 ifer;
 249         u32 ifmi;
 250         u32 ifmr;
 251         u32 ifcr0;
 252         u32 ifcr1;
 253         u32 ifcr2;
 254         u32 ifcr3;
 255         u32 ifcr4;
 256         u32 ifcr5;
 257         u32 ifcr6;
 258         u32 ifcr7;
 259         u32 ifcr8;
 260         u32 ifcr9;
 261         u32 ifcr10;
 262         u32 ifcr11;
 263         u32 ifcr12;
 264         u32 ifcr13;
 265         u32 ifcr14;
 266         u32 ifcr15;
 267         u32 gcr;
 268         u32 uartpto;
 269         u32 uartcto;
 270         u32 dmatxe;
 271         u32 dmarxe;
 272 };
 273
 274 /* MSCM Interrupt Router */
 275 struct mscm_ir {
 276         u32 cpxtype;            /* Processor x Type Register                    */
 277         u32 cpxnum;             /* Processor x Number Register                  */
 278         u32 cpxmaster;          /* Processor x Master Number Register   */
 279         u32 cpxcount;           /* Processor x Count Register                   */
 280         u32 cpxcfg0;            /* Processor x Configuration 0 Register */
 281         u32 cpxcfg1;            /* Processor x Configuration 1 Register */
 282         u32 cpxcfg2;            /* Processor x Configuration 2 Register */
 283         u32 cpxcfg3;            /* Processor x Configuration 3 Register */
 284         u32 cp0type;            /* Processor 0 Type Register                    */
 285         u32 cp0num;             /* Processor 0 Number Register                  */
 286         u32 cp0master;          /* Processor 0 Master Number Register   */
 287         u32 cp0count;           /* Processor 0 Count Register                   */
 288         u32 cp0cfg0;            /* Processor 0 Configuration 0 Register */
 289         u32 cp0cfg1;            /* Processor 0 Configuration 1 Register */
 290         u32 cp0cfg2;            /* Processor 0 Configuration 2 Register */
 291         u32 cp0cfg3;            /* Processor 0 Configuration 3 Register */
 292         u32 cp1type;            /* Processor 1 Type Register                    */
 293         u32 cp1num;             /* Processor 1 Number Register                  */
 294         u32 cp1master;          /* Processor 1 Master Number Register   */
 295         u32 cp1count;           /* Processor 1 Count Register                   */
 296         u32 cp1cfg0;            /* Processor 1 Configuration 0 Register */
 297         u32 cp1cfg1;            /* Processor 1 Configuration 1 Register */
 298         u32 cp1cfg2;            /* Processor 1 Configuration 2 Register */
 299         u32 cp1cfg3;            /* Processor 1 Configuration 3 Register */
 300         u32 reserved_0x060[232];
 301         u32 ocmdr0;             /* On-Chip Memory Descriptor Register   */
 302         u32 reserved_0x404[2];
 303         u32 ocmdr3;             /* On-Chip Memory Descriptor Register   */
 304         u32 reserved_0x410[28];
 305         u32 tcmdr[4];           /* Generic Tightly Coupled Memory Descriptor Register   */
 306         u32 reserved_0x490[28];
 307         u32 cpce0;              /* Core Parity Checking Enable Register 0                               */
 308         u32 reserved_0x504[191];
 309         u32 ircp0ir;            /* Interrupt Router CP0 Interrupt Register                              */
 310         u32 ircp1ir;            /* Interrupt Router CP1 Interrupt Register                              */
 311         u32 reserved_0x808[6];
 312         u32 ircpgir;            /* Interrupt Router CPU Generate Interrupt Register             */
 313         u32 reserved_0x824[23];
 314         u16 irsprc[176];        /* Interrupt Router Shared Peripheral Routing Control Register  */
 315         u32 reserved_0x9e0[136];
 316         u32 iahbbe0;            /* Gasket Burst Enable Register                                                 */
 317         u32 reserved_0xc04[63];
 318         u32 ipcge;              /* Interconnect Parity Checking Global Enable Register  */
 319         u32 reserved_0xd04[3];
 320         u32 ipce[4];            /* Interconnect Parity Checking Enable Register                 */
 321         u32 reserved_0xd20[8];
 322         u32 ipcgie;             /* Interconnect Parity Checking Global Injection Enable Register        */
 323         u32 reserved_0xd44[3];
 324         u32 ipcie[4];           /* Interconnect Parity Checking Injection Enable Register       */
 325 };
 326
 327 #endif /* __ASSEMBLER__ */
 328
 329 #endif /* __ASM_ARCH_IMX_REGS_H__ */