arch/arm/include/asm/arch-rockchip/cru_rk3399.h

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ASM_ARCH_CRU_RK3399_H_
   8 #define __ASM_ARCH_CRU_RK3399_H_
   9
  10 #include <common.h>
  11
  12 struct rk3399_pmucru {
  13         u32 ppll_con[6];
  14         u32 reserved[0x1a];
  15         u32 pmucru_clksel[6];
  16         u32 pmucru_clkfrac_con[2];
  17         u32 reserved2[0x18];
  18         u32 pmucru_clkgate_con[3];
  19         u32 reserved3;
  20         u32 pmucru_softrst_con[2];
  21         u32 reserved4[2];
  22         u32 pmucru_rstnhold_con[2];
  23         u32 reserved5[2];
  24         u32 pmucru_gatedis_con[2];
  25 };
  26 check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
  27
  28 struct rk3399_cru {
  29         u32 apll_l_con[6];
  30         u32 reserved[2];
  31         u32 apll_b_con[6];
  32         u32 reserved1[2];
  33         u32 dpll_con[6];
  34         u32 reserved2[2];
  35         u32 cpll_con[6];
  36         u32 reserved3[2];
  37         u32 gpll_con[6];
  38         u32 reserved4[2];
  39         u32 npll_con[6];
  40         u32 reserved5[2];
  41         u32 vpll_con[6];
  42         u32 reserved6[0x0a];
  43         u32 clksel_con[108];
  44         u32 reserved7[0x14];
  45         u32 clkgate_con[35];
  46         u32 reserved8[0x1d];
  47         u32 softrst_con[21];
  48         u32 reserved9[0x2b];
  49         u32 glb_srst_fst_value;
  50         u32 glb_srst_snd_value;
  51         u32 glb_cnt_th;
  52         u32 misc_con;
  53         u32 glb_rst_con;
  54         u32 glb_rst_st;
  55         u32 reserved10[0x1a];
  56         u32 sdmmc_con[2];
  57         u32 sdio0_con[2];
  58         u32 sdio1_con[2];
  59 };
  60 check_member(rk3399_cru, sdio1_con[1], 0x594);
  61 #define MHz             1000000
  62 #define KHz             1000
  63 #define OSC_HZ          (24*MHz)
  64 #define APLL_HZ         (600*MHz)
  65 #define GPLL_HZ         (594*MHz)
  66 #define CPLL_HZ         (384*MHz)
  67 #define PPLL_HZ         (676*MHz)
  68
  69 #define PMU_PCLK_HZ     (48*MHz)
  70
  71 #define ACLKM_CORE_HZ   (300*MHz)
  72 #define ATCLK_CORE_HZ   (300*MHz)
  73 #define PCLK_DBG_HZ     (100*MHz)
  74
  75 #define PERIHP_ACLK_HZ  (148500*KHz)
  76 #define PERIHP_HCLK_HZ  (148500*KHz)
  77 #define PERIHP_PCLK_HZ  (37125*KHz)
  78
  79 #define PERILP0_ACLK_HZ (99000*KHz)
  80 #define PERILP0_HCLK_HZ (99000*KHz)
  81 #define PERILP0_PCLK_HZ (49500*KHz)
  82
  83 #define PERILP1_HCLK_HZ (99000*KHz)
  84 #define PERILP1_PCLK_HZ (49500*KHz)
  85
  86 #define PWM_CLOCK_HZ    PMU_PCLK_HZ
  87
  88 enum apll_l_frequencies {
  89         APLL_L_1600_MHZ,
  90         APLL_L_600_MHZ,
  91 };
  92
  93 #endif  /* __ASM_ARCH_CRU_RK3399_H_ */